抄録
This paper describes a newly developed CMOS LSI DSP (FDSP3). It has a powerful multiplier, which operates at a rate of 10 M-operations/s, almost twice as fast as the fastest existing LSI DSP's. Some key techniques to attain these high performance characteristics of the DSP are described. Suitable memory capacities of the RAM and ROM were analyzed as a function of the operational capability of the DSP. These were reflected in the design of the FDSP3. To assist in the development of the program, support tools have been developed. A Pascal based cross compiler and an on-line debugging tool are described.
| 本文言語 | English |
|---|---|
| ページ（範囲） | 347-356 |
| ページ数 | 10 |
| ジャーナル | IEEE Journal on Selected Areas in Communications |
| 巻 | SAC-3 |
| 号 | 2 |
| 出版ステータス | Published - 1985 3月 |
ASJC Scopus subject areas
- コンピュータ ネットワークおよび通信
- 電子工学および電気工学