抄録
Band matrix multiplication is widely used in DSP systems. However traditional Kung-Leiserson systolic array for band matrix multiplication cannot be realized with high cell-efficiency. In this paper, three high-performance band matrix multiplication systolic arrays (BMMSA) are presented based on the ideas of "Matrix Compression" and "Super Pipelined". These new systolic arrays are realized by compressing the data matrix skillfully and adjusting the operation sequence carefully. The results show that the best systolic array for band matrix multiplication uses almost 100% processing elements(PE) in each step. Also, these modifications increase the operation speed and at best spend only 1/3 processing time to complete the multiplication operation.
| 本文言語 | English |
|---|---|
| ホスト出版物のタイトル | Proceedings - IEEE International Symposium on Circuits and Systems |
| ページ | 1130-1133 |
| ページ数 | 4 |
| DOI | |
| 出版ステータス | Published - 2005 |
| イベント | IEEE International Symposium on Circuits and Systems 2005, ISCAS 2005 - Kobe, Japan 継続期間: 2005 5月 23 → 2005 5月 26 |
Other
| Other | IEEE International Symposium on Circuits and Systems 2005, ISCAS 2005 |
|---|---|
| 国/地域 | Japan |
| City | Kobe |
| Period | 05/5/23 → 05/5/26 |
ASJC Scopus subject areas
- 電子工学および電気工学