抄録
The thermal problem is a challenge in recent Network on Chip (NoC) designs due to its great impact on the network performance and reliability, especially for 3D NoC. In this work, we design a virtual channel based fully adaptive routing algorithm for the runtime 3D NoC thermal-aware management. For throttling information collection, instead of transmitting the topology information of the whole network, we use a 12 bits register to reserve the router state for one hop away instead of transmitting the topology information of the whole network. It saves the hardware cost largely and decreases the network latency. To ensure deadlock and livelock free and minimize the hardware overhead, we only use two virtual channels for each horizontal channel to achieve full adaptivity and high routability. For path selection, we design a strategy that takes priority to the distance, but also consider path diversity and traffic state. Experimental results show that the proposed algorithm shows better network latency and throughput with low power compared with traditional algorithms.
本文言語 | English |
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ホスト出版物のタイトル | Proceedings of the 18th International Symposium on Quality Electronic Design, ISQED 2017 |
出版社 | IEEE Computer Society |
ページ | 289-295 |
ページ数 | 7 |
ISBN(電子版) | 9781509054046 |
DOI | |
出版ステータス | Published - 2017 5月 2 |
イベント | 18th International Symposium on Quality Electronic Design, ISQED 2017 - Santa Clara, United States 継続期間: 2017 3月 14 → 2017 3月 15 |
Other
Other | 18th International Symposium on Quality Electronic Design, ISQED 2017 |
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国/地域 | United States |
City | Santa Clara |
Period | 17/3/14 → 17/3/15 |
ASJC Scopus subject areas
- ハードウェアとアーキテクチャ
- 電子工学および電気工学
- 安全性、リスク、信頼性、品質管理