High speed page mode sensing scheme for EPROM's and flash EEPROM's using divided bit line architecture

Yasushi Terada; Takeshi Nakayama; Kazuo Kobayashi; Masanori Hayashikoshi; Shin ichi Kobayashi; Yoshikazu Miyawaki; Natsuo Ajika; Hideaki Arima; Tsutomu Yoshihara

High speed page mode sensing scheme for EPROM's and flash EEPROM's using divided bit line architecture

Yasushi Terada^*, Takeshi Nakayama, Kazuo Kobayashi, Masanori Hayashikoshi, Shin ichi Kobayashi, Yoshikazu Miyawaki, Natsuo Ajika, Hideaki Arima, Tsutomu Yoshihara

^*この研究の対応する著者

研究成果: Conference contribution

抄録

A novel high-speed page mode sense scheme for EPROMs and flash EEPROMs has been developed. A divided bit line architecture makes it possible to adopt a folded bit line architecture in which sense amplifiers are located at the end of the bit lines. Dynamic sensing avoids the soft write problem by reducing bit line voltage and the current flow through the memory cell. An experimental 1-Mb flash EEPROM using a 0.6-μm design rule has been designed. Simulated results show that a high-speed address access time of 60 ns and a page mode access time of 15 ns can be achieved.

本文言語	English
ホスト出版物のタイトル	90 Symp VLSI Circuits
Place of Publication	Piscataway, NJ, United States
出版社	Publ by IEEE
ページ	97-98
ページ数	2
出版ステータス	Published - 1990
外部発表	はい
イベント	1990 Symposium on VLSI Circuits - Honolulu, HI, USA 継続期間: 1990 6月 7 → 1990 6月 9

Other

Other	1990 Symposium on VLSI Circuits
City	Honolulu, HI, USA
Period	90/6/7 → 90/6/9

ASJC Scopus subject areas

工学（全般）

他のファイルとリンク

引用スタイル

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title = "High speed page mode sensing scheme for EPROM's and flash EEPROM's using divided bit line architecture",

abstract = "A novel high-speed page mode sense scheme for EPROMs and flash EEPROMs has been developed. A divided bit line architecture makes it possible to adopt a folded bit line architecture in which sense amplifiers are located at the end of the bit lines. Dynamic sensing avoids the soft write problem by reducing bit line voltage and the current flow through the memory cell. An experimental 1-Mb flash EEPROM using a 0.6-μm design rule has been designed. Simulated results show that a high-speed address access time of 60 ns and a page mode access time of 15 ns can be achieved.",

author = "Yasushi Terada and Takeshi Nakayama and Kazuo Kobayashi and Masanori Hayashikoshi and Kobayashi, {Shin ichi} and Yoshikazu Miyawaki and Natsuo Ajika and Hideaki Arima and Tsutomu Yoshihara",

year = "1990",

language = "English",

pages = "97--98",

booktitle = "90 Symp VLSI Circuits",

publisher = "Publ by IEEE",

note = "1990 Symposium on VLSI Circuits ; Conference date: 07-06-1990 Through 09-06-1990",

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T1 - High speed page mode sensing scheme for EPROM's and flash EEPROM's using divided bit line architecture

AU - Terada, Yasushi

AU - Nakayama, Takeshi

AU - Kobayashi, Kazuo

AU - Hayashikoshi, Masanori

AU - Kobayashi, Shin ichi

AU - Miyawaki, Yoshikazu

AU - Ajika, Natsuo

AU - Arima, Hideaki

AU - Yoshihara, Tsutomu

PY - 1990

Y1 - 1990

N2 - A novel high-speed page mode sense scheme for EPROMs and flash EEPROMs has been developed. A divided bit line architecture makes it possible to adopt a folded bit line architecture in which sense amplifiers are located at the end of the bit lines. Dynamic sensing avoids the soft write problem by reducing bit line voltage and the current flow through the memory cell. An experimental 1-Mb flash EEPROM using a 0.6-μm design rule has been designed. Simulated results show that a high-speed address access time of 60 ns and a page mode access time of 15 ns can be achieved.

AB - A novel high-speed page mode sense scheme for EPROMs and flash EEPROMs has been developed. A divided bit line architecture makes it possible to adopt a folded bit line architecture in which sense amplifiers are located at the end of the bit lines. Dynamic sensing avoids the soft write problem by reducing bit line voltage and the current flow through the memory cell. An experimental 1-Mb flash EEPROM using a 0.6-μm design rule has been designed. Simulated results show that a high-speed address access time of 60 ns and a page mode access time of 15 ns can be achieved.

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M3 - Conference contribution

AN - SCOPUS:0025559292

SP - 97

EP - 98

BT - 90 Symp VLSI Circuits

PB - Publ by IEEE

CY - Piscataway, NJ, United States

T2 - 1990 Symposium on VLSI Circuits

Y2 - 7 June 1990 through 9 June 1990

ER -

High speed page mode sensing scheme for EPROM's and flash EEPROM's using divided bit line architecture

抄録

Other

ASJC Scopus subject areas

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