Highly linear high isolation SPDT switch IC with back-gate effect and floating body technique in 180-nm CMOS

Xiao Xu; Xin Yang; Zheng Sun; Taufiq Alif Kurniawan; Toshihiko Yoshimasu

doi:10.1109/RFIT.2015.7377902

Highly linear high isolation SPDT switch IC with back-gate effect and floating body technique in 180-nm CMOS

Xiao Xu, Xin Yang, Zheng Sun, Taufiq Alif Kurniawan, Toshihiko Yoshimasu

大学院情報生産システム研究科

研究成果: Conference contribution

6 被引用数 (Scopus)

抄録

This paper presents a broadband single-pole double-throw (SPDT) switch IC in a 180-nm CMOS process. Back-gate voltage injection and floating body technique are utilized to improve the power handling capability, insertion loss and isolation performance, simultaneously. The fabricated SPDT switch IC has exhibited an input referred 0.3-dB compression point of 21.0 dBm, an isolation of 42.7 dB and an insertion loss of 1.1 dB for transmit mode at an operation frequency of 5.0 GHz.

本文言語	English
ホスト出版物のタイトル	2015 IEEE International Symposium on Radio-Frequency Integration Technology, RFIT 2015 - Proceedings
出版社	Institute of Electrical and Electronics Engineers Inc.
ページ	106-108
ページ数	3
ISBN（電子版）	9781467377942
DOI	https://doi.org/10.1109/RFIT.2015.7377902
出版ステータス	Published - 2016 1月 8
イベント	IEEE International Symposium on Radio-Frequency Integration Technology, RFIT 2015 - Sendai, Japan 継続期間: 2015 8月 26 → 2015 8月 28

出版物シリーズ

名前	2015 IEEE International Symposium on Radio-Frequency Integration Technology, RFIT 2015 - Proceedings

Other

Other	IEEE International Symposium on Radio-Frequency Integration Technology, RFIT 2015
国/地域	Japan
City	Sendai
Period	15/8/26 → 15/8/28

ASJC Scopus subject areas

コンピュータネットワークおよび通信
電子工学および電気工学

文献へのアクセス

10.1109/RFIT.2015.7377902

他のファイルとリンク

引用スタイル

Xu, X., Yang, X., Sun, Z., Kurniawan, T. A., & Yoshimasu, T. (2016). Highly linear high isolation SPDT switch IC with back-gate effect and floating body technique in 180-nm CMOS. In 2015 IEEE International Symposium on Radio-Frequency Integration Technology, RFIT 2015 - Proceedings (pp. 106-108). [7377902] (2015 IEEE International Symposium on Radio-Frequency Integration Technology, RFIT 2015 - Proceedings). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/RFIT.2015.7377902

Highly linear high isolation SPDT switch IC with back-gate effect and floating body technique in 180-nm CMOS. / Xu, Xiao; Yang, Xin; Sun, Zheng その他.
2015 IEEE International Symposium on Radio-Frequency Integration Technology, RFIT 2015 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 2016. p. 106-108 7377902 (2015 IEEE International Symposium on Radio-Frequency Integration Technology, RFIT 2015 - Proceedings).

研究成果: Conference contribution

Xu, X, Yang, X, Sun, Z, Kurniawan, TA & Yoshimasu, T 2016, Highly linear high isolation SPDT switch IC with back-gate effect and floating body technique in 180-nm CMOS. in 2015 IEEE International Symposium on Radio-Frequency Integration Technology, RFIT 2015 - Proceedings., 7377902, 2015 IEEE International Symposium on Radio-Frequency Integration Technology, RFIT 2015 - Proceedings, Institute of Electrical and Electronics Engineers Inc., pp. 106-108, IEEE International Symposium on Radio-Frequency Integration Technology, RFIT 2015, Sendai, Japan, 15/8/26. https://doi.org/10.1109/RFIT.2015.7377902

Xu X, Yang X, Sun Z, Kurniawan TA, Yoshimasu T. Highly linear high isolation SPDT switch IC with back-gate effect and floating body technique in 180-nm CMOS. In 2015 IEEE International Symposium on Radio-Frequency Integration Technology, RFIT 2015 - Proceedings. Institute of Electrical and Electronics Engineers Inc. 2016. p. 106-108. 7377902. (2015 IEEE International Symposium on Radio-Frequency Integration Technology, RFIT 2015 - Proceedings). doi: 10.1109/RFIT.2015.7377902

Xu, Xiao ; Yang, Xin ; Sun, Zheng その他. / Highly linear high isolation SPDT switch IC with back-gate effect and floating body technique in 180-nm CMOS. 2015 IEEE International Symposium on Radio-Frequency Integration Technology, RFIT 2015 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 2016. pp. 106-108 (2015 IEEE International Symposium on Radio-Frequency Integration Technology, RFIT 2015 - Proceedings).

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title = "Highly linear high isolation SPDT switch IC with back-gate effect and floating body technique in 180-nm CMOS",

abstract = "This paper presents a broadband single-pole double-throw (SPDT) switch IC in a 180-nm CMOS process. Back-gate voltage injection and floating body technique are utilized to improve the power handling capability, insertion loss and isolation performance, simultaneously. The fabricated SPDT switch IC has exhibited an input referred 0.3-dB compression point of 21.0 dBm, an isolation of 42.7 dB and an insertion loss of 1.1 dB for transmit mode at an operation frequency of 5.0 GHz.",

keywords = "Back-gate effect, Broadband, Floating body technique, High isolation, High power handling capability, SPDT switch IC",

author = "Xiao Xu and Xin Yang and Zheng Sun and Kurniawan, {Taufiq Alif} and Toshihiko Yoshimasu",

note = "Funding Information: ACKNOWLEDGMENT This work is supported by VDEC, University of Tokyo in collaboration with Cadence Design Systems inc, Mentor Graphics inc, and Agilent Technologies Japan Ltd. Publisher Copyright: {\textcopyright} 2015 IEEE.; IEEE International Symposium on Radio-Frequency Integration Technology, RFIT 2015 ; Conference date: 26-08-2015 Through 28-08-2015",

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AU - Kurniawan, Taufiq Alif

AU - Yoshimasu, Toshihiko

N1 - Funding Information: ACKNOWLEDGMENT This work is supported by VDEC, University of Tokyo in collaboration with Cadence Design Systems inc, Mentor Graphics inc, and Agilent Technologies Japan Ltd. Publisher Copyright: © 2015 IEEE.

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N2 - This paper presents a broadband single-pole double-throw (SPDT) switch IC in a 180-nm CMOS process. Back-gate voltage injection and floating body technique are utilized to improve the power handling capability, insertion loss and isolation performance, simultaneously. The fabricated SPDT switch IC has exhibited an input referred 0.3-dB compression point of 21.0 dBm, an isolation of 42.7 dB and an insertion loss of 1.1 dB for transmit mode at an operation frequency of 5.0 GHz.

AB - This paper presents a broadband single-pole double-throw (SPDT) switch IC in a 180-nm CMOS process. Back-gate voltage injection and floating body technique are utilized to improve the power handling capability, insertion loss and isolation performance, simultaneously. The fabricated SPDT switch IC has exhibited an input referred 0.3-dB compression point of 21.0 dBm, an isolation of 42.7 dB and an insertion loss of 1.1 dB for transmit mode at an operation frequency of 5.0 GHz.

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Highly linear high isolation SPDT switch IC with back-gate effect and floating body technique in 180-nm CMOS

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出版物シリーズ

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ASJC Scopus subject areas

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