TY - GEN
T1 - Highly parallel fractional motion estimation engine for Super Hi-Vision 4k×4k@60fps
AU - Huang, Yiqing
AU - Liu, Qin
AU - Ikenaga, Takeshi
PY - 2009/12/1
Y1 - 2009/12/1
N2 - One Super Hi-Vision (SHV) 4k×4k@60fps fractional motion estimation (FME) engine is proposed in our paper. Firstly, two complexity reduction schemes are proposed in the algorithm level. By analyzing the integer motion cost, 48% clock cycle is saved based on our mode pre-filtering scheme. By further check the motion cost of neighboring search points, our directional one-pass scheme can achieve reduction of 50% clock cycle and 36% hardware cost. Secondly, in the hardware level, two parallel improved schemes namely 16-Pel interpolation and MB-parallel processing are given out. Thirdly, one unified pixel block loading scheme is proposed. About 28.67% to 80.68% pixels are reused and the related memory access is saved. Furthermore, one parity pixel organization scheme is proposed to solve memory access conflict of MB-parallel processing. By using TSMC 0.18μm technology in worst work conditions (1.62V, 125°C), our FME engine can achieve real-time processing for SHV 4k×4k@60fps with 976.5k gates hardware.
AB - One Super Hi-Vision (SHV) 4k×4k@60fps fractional motion estimation (FME) engine is proposed in our paper. Firstly, two complexity reduction schemes are proposed in the algorithm level. By analyzing the integer motion cost, 48% clock cycle is saved based on our mode pre-filtering scheme. By further check the motion cost of neighboring search points, our directional one-pass scheme can achieve reduction of 50% clock cycle and 36% hardware cost. Secondly, in the hardware level, two parallel improved schemes namely 16-Pel interpolation and MB-parallel processing are given out. Thirdly, one unified pixel block loading scheme is proposed. About 28.67% to 80.68% pixels are reused and the related memory access is saved. Furthermore, one parity pixel organization scheme is proposed to solve memory access conflict of MB-parallel processing. By using TSMC 0.18μm technology in worst work conditions (1.62V, 125°C), our FME engine can achieve real-time processing for SHV 4k×4k@60fps with 976.5k gates hardware.
UR - http://www.scopus.com/inward/record.url?scp=74349120940&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=74349120940&partnerID=8YFLogxK
U2 - 10.1109/MMSP.2009.5293323
DO - 10.1109/MMSP.2009.5293323
M3 - Conference contribution
AN - SCOPUS:74349120940
SN - 9781424444649
T3 - 2009 IEEE International Workshop on Multimedia Signal Processing, MMSP '09
BT - 2009 IEEE International Workshop on Multimedia Signal Processing, MMSP '09
T2 - 2009 IEEE International Workshop on Multimedia Signal Processing, MMSP '09
Y2 - 5 October 2009 through 7 October 2009
ER -