抄録
Networks-on-Chip (NoCs) offers considerable performance improvement to Chip Multi-Processors (CMPs). As the communication between processors on NoC increases, its system performance faces a severe challenge in congestion issues. Adaptive routing algorithm for NoCs provides a variety of path options, thus, it has fantastic potential to achieve better traffic distribution across the network by avoiding the congested regions. An excellent output selection method can realize the potential of adaptive routing algorithm as highly as possible. Therefore, designing an efficient output selection method is highly desirable. Conventional output selection methods only consider local information (buffer vacancy) or global information (path diversity) separately, which makes them difficult to spread traffic to different paths for load balance. In this paper, we propose an efficient output selection method integrating global information of path diversity and local information of buffer vacancy, to solve congestion problem in NoCs.
本文言語 | English |
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ホスト出版物のタイトル | Proceedings - International SoC Design Conference 2017, ISOCC 2017 |
出版社 | Institute of Electrical and Electronics Engineers Inc. |
ページ | 125-126 |
ページ数 | 2 |
ISBN(電子版) | 9781538622858 |
DOI | |
出版ステータス | Published - 2018 5月 29 |
イベント | 14th International SoC Design Conference, ISOCC 2017 - Seoul, Korea, Republic of 継続期間: 2017 11月 5 → 2017 11月 8 |
Other
Other | 14th International SoC Design Conference, ISOCC 2017 |
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国/地域 | Korea, Republic of |
City | Seoul |
Period | 17/11/5 → 17/11/8 |
ASJC Scopus subject areas
- ハードウェアとアーキテクチャ
- 電子工学および電気工学
- 電子材料、光学材料、および磁性材料