Image synthesis circuit design using selector-logic-based alpha blending and its FPGA implementation

Keita Igarashi; Masao Yanagisawa; Nozomu Togawa

doi:10.1109/ASICON.2015.7517027

Image synthesis circuit design using selector-logic-based alpha blending and its FPGA implementation

Keita Igarashi, Masao Yanagisawa, Nozomu Togawa

研究成果: Conference contribution

3 被引用数 (Scopus)

抄録

Alpha blending is one of image synthesis techniques, which synthesizes a new image by summing up weighted input images and realizes transparent effect. In this paper, we focus on alpha blending using selector logics and implement it on an FPGA board. By applying selector logics to the alpha blending operation, its total product terms are decreased and thus a circuit size and circuit delay are improved simultaneously. In our implementation, original pixel values are stored into a memory on the FPGA board and then a new pixel value is synthesized based on input transmittance factors. We realize approximately 23% speed-up and 8% area reduction simultaneously using selector-logic based alpha blending.

本文言語	English
ホスト出版物のタイトル	Proceedings - 2015 IEEE 11th International Conference on ASIC, ASICON 2015
出版社	Institute of Electrical and Electronics Engineers Inc.
ISBN（電子版）	9781479984831
DOI	https://doi.org/10.1109/ASICON.2015.7517027
出版ステータス	Published - 2016 7月 19
イベント	11th IEEE International Conference on Advanced Semiconductor Integrated Circuits (ASIC), ASICON 2015 - Chengdu, China 継続期間: 2015 11月 3 → 2015 11月 6

Other

Other	11th IEEE International Conference on Advanced Semiconductor Integrated Circuits (ASIC), ASICON 2015
国/地域	China
City	Chengdu
Period	15/11/3 → 15/11/6

ASJC Scopus subject areas

ハードウェアとアーキテクチャ
電子工学および電気工学

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10.1109/ASICON.2015.7517027

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引用スタイル

Igarashi, K, Yanagisawa, M & Togawa, N 2016, Image synthesis circuit design using selector-logic-based alpha blending and its FPGA implementation. in Proceedings - 2015 IEEE 11th International Conference on ASIC, ASICON 2015., 7517027, Institute of Electrical and Electronics Engineers Inc., 11th IEEE International Conference on Advanced Semiconductor Integrated Circuits (ASIC), ASICON 2015, Chengdu, China, 15/11/3. https://doi.org/10.1109/ASICON.2015.7517027

@inproceedings{0c874a567f7f405992234b98738b7c64,

title = "Image synthesis circuit design using selector-logic-based alpha blending and its FPGA implementation",

abstract = "Alpha blending is one of image synthesis techniques, which synthesizes a new image by summing up weighted input images and realizes transparent effect. In this paper, we focus on alpha blending using selector logics and implement it on an FPGA board. By applying selector logics to the alpha blending operation, its total product terms are decreased and thus a circuit size and circuit delay are improved simultaneously. In our implementation, original pixel values are stored into a memory on the FPGA board and then a new pixel value is synthesized based on input transmittance factors. We realize approximately 23% speed-up and 8% area reduction simultaneously using selector-logic based alpha blending.",

author = "Keita Igarashi and Masao Yanagisawa and Nozomu Togawa",

year = "2016",

month = jul,

day = "19",

doi = "10.1109/ASICON.2015.7517027",

language = "English",

booktitle = "Proceedings - 2015 IEEE 11th International Conference on ASIC, ASICON 2015",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

address = "United States",

note = "11th IEEE International Conference on Advanced Semiconductor Integrated Circuits (ASIC), ASICON 2015 ; Conference date: 03-11-2015 Through 06-11-2015",

}

TY - GEN

T1 - Image synthesis circuit design using selector-logic-based alpha blending and its FPGA implementation

AU - Igarashi, Keita

AU - Yanagisawa, Masao

AU - Togawa, Nozomu

PY - 2016/7/19

Y1 - 2016/7/19

N2 - Alpha blending is one of image synthesis techniques, which synthesizes a new image by summing up weighted input images and realizes transparent effect. In this paper, we focus on alpha blending using selector logics and implement it on an FPGA board. By applying selector logics to the alpha blending operation, its total product terms are decreased and thus a circuit size and circuit delay are improved simultaneously. In our implementation, original pixel values are stored into a memory on the FPGA board and then a new pixel value is synthesized based on input transmittance factors. We realize approximately 23% speed-up and 8% area reduction simultaneously using selector-logic based alpha blending.

AB - Alpha blending is one of image synthesis techniques, which synthesizes a new image by summing up weighted input images and realizes transparent effect. In this paper, we focus on alpha blending using selector logics and implement it on an FPGA board. By applying selector logics to the alpha blending operation, its total product terms are decreased and thus a circuit size and circuit delay are improved simultaneously. In our implementation, original pixel values are stored into a memory on the FPGA board and then a new pixel value is synthesized based on input transmittance factors. We realize approximately 23% speed-up and 8% area reduction simultaneously using selector-logic based alpha blending.

UR - http://www.scopus.com/inward/record.url?scp=84982283255&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84982283255&partnerID=8YFLogxK

U2 - 10.1109/ASICON.2015.7517027

DO - 10.1109/ASICON.2015.7517027

M3 - Conference contribution

AN - SCOPUS:84982283255

BT - Proceedings - 2015 IEEE 11th International Conference on ASIC, ASICON 2015

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 11th IEEE International Conference on Advanced Semiconductor Integrated Circuits (ASIC), ASICON 2015

Y2 - 3 November 2015 through 6 November 2015

ER -

Image synthesis circuit design using selector-logic-based alpha blending and its FPGA implementation

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