A hybrid-trench-isolation (HTI) technology is proposed to overcome the scaling limitations caused by the difficulty of gate thinning and increased soft error rate at the 0.1 μm era. It is revealed that a significant speed improvement against bulk is achieved by using the body-tied structure without floating-body-related speed deterioration. A two-order reduction in the soft error rate for an HTI-SOI 4M-bit SRAM was demonstrated as compared with bulk one. Moreover, it is presented that full trench isolation in the HTI offers excellent isolation characteristics to realize the one-chip integration of analog and digital LSI's. It is concluded that SOI technology with the HTI structure is one of the solutions against the scaling limitations.
|ジャーナル||Technical Digest - International Electron Devices Meeting|
|出版ステータス||Published - 2000|
|イベント||2000 IEEE International Electron Devices Meeting - San Francisco, CA, United States|
継続期間: 2000 12月 10 → 2000 12月 13
ASJC Scopus subject areas