Impact of 0.18 μm SOI CMOS technology using hybrid trench isolation with high resistivity substrate on embedded RF/analog applications

S. Maeda; Y. Wada; K. Yamamoto; H. Komurasaki; T. Matsumoto; Y. Hirano; T. Iwamatsu; Y. Yamaguchi; T. Ipposhi; K. Ueda; K. Mashiko; S. Maegawa; M. Inuishi

Impact of 0.18 μm SOI CMOS technology using hybrid trench isolation with high resistivity substrate on embedded RF/analog applications

S. Maeda^*, Y. Wada, K. Yamamoto, H. Komurasaki, T. Matsumoto, Y. Hirano, T. Iwamatsu, Y. Yamaguchi, T. Ipposhi, K. Ueda, K. Mashiko, S. Maegawa, M. Inuishi

^*この研究の対応する著者

研究成果: Conference article › 査読

14 被引用数 (Scopus)

抄録

A 0.18 μm silicon on insulator (SOI) CMOS using hybrid trench isolation with high resistivity substrate (HRS) is proposed and revealed its impact on high performance embedded RF/analog applications. Using this technology, advantages of SOI MOSFETs due to the reduction of power loss is proven. Then, excellent body-fixing capability of this SOI MOSFET and high-quality on-chip inductance is demonstrated for RF/analog LSIs.

本文言語	English
ページ（範囲）	154-155
ページ数	2
ジャーナル	Digest of Technical Papers - Symposium on VLSI Technology
出版ステータス	Published - 2000
外部発表	はい
イベント	2000 Symposium on VLSI Technology - Honolulu, HI, USA 継続期間: 2000 6月 13 → 2000 6月 15

ASJC Scopus subject areas

電子工学および電気工学

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引用スタイル

Maeda, S., Wada, Y., Yamamoto, K., Komurasaki, H., Matsumoto, T., Hirano, Y., Iwamatsu, T., Yamaguchi, Y., Ipposhi, T., Ueda, K., Mashiko, K., Maegawa, S., & Inuishi, M. (2000). Impact of 0.18 μm SOI CMOS technology using hybrid trench isolation with high resistivity substrate on embedded RF/analog applications. Digest of Technical Papers - Symposium on VLSI Technology, 154-155.

Maeda, S, Wada, Y, Yamamoto, K, Komurasaki, H, Matsumoto, T, Hirano, Y, Iwamatsu, T, Yamaguchi, Y, Ipposhi, T, Ueda, K, Mashiko, K, Maegawa, S & Inuishi, M 2000, 'Impact of 0.18 μm SOI CMOS technology using hybrid trench isolation with high resistivity substrate on embedded RF/analog applications', Digest of Technical Papers - Symposium on VLSI Technology, pp. 154-155.

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abstract = "A 0.18 μm silicon on insulator (SOI) CMOS using hybrid trench isolation with high resistivity substrate (HRS) is proposed and revealed its impact on high performance embedded RF/analog applications. Using this technology, advantages of SOI MOSFETs due to the reduction of power loss is proven. Then, excellent body-fixing capability of this SOI MOSFET and high-quality on-chip inductance is demonstrated for RF/analog LSIs.",

author = "S. Maeda and Y. Wada and K. Yamamoto and H. Komurasaki and T. Matsumoto and Y. Hirano and T. Iwamatsu and Y. Yamaguchi and T. Ipposhi and K. Ueda and K. Mashiko and S. Maegawa and M. Inuishi",

year = "2000",

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journal = "Digest of Technical Papers - Symposium on VLSI Technology",

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T1 - Impact of 0.18 μm SOI CMOS technology using hybrid trench isolation with high resistivity substrate on embedded RF/analog applications

AU - Maeda, S.

AU - Wada, Y.

AU - Yamamoto, K.

AU - Komurasaki, H.

AU - Matsumoto, T.

AU - Hirano, Y.

AU - Iwamatsu, T.

AU - Yamaguchi, Y.

AU - Ipposhi, T.

AU - Ueda, K.

AU - Mashiko, K.

AU - Maegawa, S.

AU - Inuishi, M.

PY - 2000

Y1 - 2000

N2 - A 0.18 μm silicon on insulator (SOI) CMOS using hybrid trench isolation with high resistivity substrate (HRS) is proposed and revealed its impact on high performance embedded RF/analog applications. Using this technology, advantages of SOI MOSFETs due to the reduction of power loss is proven. Then, excellent body-fixing capability of this SOI MOSFET and high-quality on-chip inductance is demonstrated for RF/analog LSIs.

AB - A 0.18 μm silicon on insulator (SOI) CMOS using hybrid trench isolation with high resistivity substrate (HRS) is proposed and revealed its impact on high performance embedded RF/analog applications. Using this technology, advantages of SOI MOSFETs due to the reduction of power loss is proven. Then, excellent body-fixing capability of this SOI MOSFET and high-quality on-chip inductance is demonstrated for RF/analog LSIs.

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M3 - Conference article

AN - SCOPUS:0033682238

SN - 0743-1562

SP - 154

EP - 155

JO - Digest of Technical Papers - Symposium on VLSI Technology

JF - Digest of Technical Papers - Symposium on VLSI Technology

T2 - 2000 Symposium on VLSI Technology

Y2 - 13 June 2000 through 15 June 2000

ER -