TY - JOUR
T1 - Improved launch for higher TDF coverage with fewer test patterns
AU - Shi, Youhua
AU - Togawa, Nozomu
AU - Yanagisawa, Masao
AU - Ohtsuki, Tatsuo
PY - 2010/8/1
Y1 - 2010/8/1
N2 - Due to the limitations of scan structure, the second vector in transition delay test is usually applied either by shift operation or by functional launch, which possibly results in unsatisfying transition delay fault (TDF) coverage. To overcome such a limitation for higher TDF coverage, a novel improved launch delay test technique that combines the pros of launch-on-shift and launch-on-capture tests is introduced in this paper. The proposed method can achieve near perfect TDF coverage with fewer test patterns without the need for a global fast scan enable signal. Experimental results on ISCAS89 and ITC99 benchmark circuits are included to show the effectiveness of the proposed method.
AB - Due to the limitations of scan structure, the second vector in transition delay test is usually applied either by shift operation or by functional launch, which possibly results in unsatisfying transition delay fault (TDF) coverage. To overcome such a limitation for higher TDF coverage, a novel improved launch delay test technique that combines the pros of launch-on-shift and launch-on-capture tests is introduced in this paper. The proposed method can achieve near perfect TDF coverage with fewer test patterns without the need for a global fast scan enable signal. Experimental results on ISCAS89 and ITC99 benchmark circuits are included to show the effectiveness of the proposed method.
KW - Design for testability
KW - transition delay testing
KW - transitional delay test coverage
UR - http://www.scopus.com/inward/record.url?scp=77954873052&partnerID=8YFLogxK
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U2 - 10.1109/TCAD.2010.2047475
DO - 10.1109/TCAD.2010.2047475
M3 - Article
AN - SCOPUS:77954873052
SN - 0278-0070
VL - 29
SP - 1294
EP - 1299
JO - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
JF - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IS - 8
M1 - 5512687
ER -