抄録
As process technology is scaling down, timing speculation techniques such as Razor and STEP are emerged as alternative solutions to reduce required margins due to various variation effects. Unlike Razor, STEP is a prediction-based timing speculation method to predict suspicious timing errors before they really appear, and thus it can result in more performance improvement. Therefore, an improved monitoring-path selection algorithm for STEP-based timing speculation is proposed in this paper, in which candidate monitoring-paths are selected based on short path removement and path length estimation. Experimental results show that the proposed algorithm realizes an average of 1.71X overclocking compared with worst-case based designs.
本文言語 | English |
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ホスト出版物のタイトル | Proceedings - 2015 IEEE 11th International Conference on ASIC, ASICON 2015 |
出版社 | Institute of Electrical and Electronics Engineers Inc. |
ISBN(電子版) | 9781479984831 |
DOI | |
出版ステータス | Published - 2016 7月 19 |
イベント | 11th IEEE International Conference on Advanced Semiconductor Integrated Circuits (ASIC), ASICON 2015 - Chengdu, China 継続期間: 2015 11月 3 → 2015 11月 6 |
Other
Other | 11th IEEE International Conference on Advanced Semiconductor Integrated Circuits (ASIC), ASICON 2015 |
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国/地域 | China |
City | Chengdu |
Period | 15/11/3 → 15/11/6 |
ASJC Scopus subject areas
- ハードウェアとアーキテクチャ
- 電子工学および電気工学