抄録
As technology advances, 3D ICs are introduced for alleviating the interconnect problem coming with shrinking feature size and increasing integration density. In 3D ICs, one of the key challenges is the vertical interlayer via used for different device layers connection. In this paper, we use min-cost maximum flow algorithm for integrated interlayer via planning and pin assignment for all two-pin nets from one source block to all the other blocks, which make sure interlayer via is inserted as successfully as possible with the shortest wire length. By iteratively using this algorithm with other auxiliary methods on each block, we can deal with the problem for all nets among blocks in 3D ICs. Experimental results show its efficiency and effectiveness. To our knowledge, this is the first algorithm of interlayer via planning with pin assignment for 3D ICs.
| 本文言語 | English |
|---|---|
| ホスト出版物のタイトル | International Workshop on System Level Interconnect Prediction, SLIP |
| ページ | 99-104 |
| ページ数 | 6 |
| DOI | |
| 出版ステータス | Published - 2009 |
| イベント | 2009 ACM/IEEE Workshop on System Level Interconnect Prediction, SLIP'09 - San Francisco, CA 継続期間: 2009 7月 26 → 2009 7月 27 |
Other
| Other | 2009 ACM/IEEE Workshop on System Level Interconnect Prediction, SLIP'09 |
|---|---|
| City | San Francisco, CA |
| Period | 09/7/26 → 09/7/27 |
ASJC Scopus subject areas
- ハードウェアとアーキテクチャ
- 電子工学および電気工学
- コンピュータ サイエンスの応用
- 応用数学
UN SDG
この成果は、次の持続可能な開発目標に貢献しています
