Memory array architecture and decoding scheme for 3V only sector erasable DINOR flash memory

Shi ichi Kobayashi; Hiroaki Nakat; Yuichi Kunori; Takeshi Nakayama; Yoshikazu Miyawaki; Yasushi Terada; Hiroshi Onoda; Natsuo Ajika; Masahiro Hatanaka; Hirokazu Misyoshi; Tsutomu Yoshihara

Memory array architecture and decoding scheme for 3V only sector erasable DINOR flash memory

Shi ichi Kobayashi^*, Hiroaki Nakat, Yuichi Kunori, Takeshi Nakayama, Yoshikazu Miyawaki, Yasushi Terada, Hiroshi Onoda, Natsuo Ajika, Masahiro Hatanaka, Hirokazu Misyoshi, Tsutomu Yoshihara

^*この研究の対応する著者

研究成果: Conference contribution

3 被引用数 (Scopus)

抄録

Several memory array configurations have been proposed for single power supply flash memories. This scheme realizes 1K byte sector erasure with minimized disturbance to the unselected sectors. A memory array configuration and a decoder circuits for the DINOR flash memory have been described. The hierarchical row decoder and the compact source line driver realize 1K byte sector erasure without increasing the decoder area. The decoder pitch has been relaxed to one driver per two word lines. Narrow threshold voltage distribution has been realized by the bit-by-bit programming control and the low threshold voltage detection circuit, which achieves high speed random access time t low V_cc .

本文言語	English
ホスト出版物のタイトル	1993 Symposium on VLSI Circuits Digest of Technical Papers
Place of Publication	Piscataway, NJ, United States
出版社	Publ by IEEE
ページ	97-98
ページ数	2
ISBN（印刷版）	0780312619
出版ステータス	Published - 1993
外部発表	はい
イベント	1993 Symposium on VLSI Circuits Digest of Technical Papers - Kyoto, Jpn 継続期間: 1993 5月 19 → 1993 5月 21

Other

Other	1993 Symposium on VLSI Circuits Digest of Technical Papers
City	Kyoto, Jpn
Period	93/5/19 → 93/5/21

ASJC Scopus subject areas

工学（全般）

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引用スタイル

Kobayashi, SI, Nakat, H, Kunori, Y, Nakayama, T, Miyawaki, Y, Terada, Y, Onoda, H, Ajika, N, Hatanaka, M, Misyoshi, H & Yoshihara, T 1993, Memory array architecture and decoding scheme for 3V only sector erasable DINOR flash memory. in 1993 Symposium on VLSI Circuits Digest of Technical Papers. Publ by IEEE, Piscataway, NJ, United States, pp. 97-98, 1993 Symposium on VLSI Circuits Digest of Technical Papers, Kyoto, Jpn, 93/5/19.

@inproceedings{be2827a304b440e49d807174c08660b5,

title = "Memory array architecture and decoding scheme for 3V only sector erasable DINOR flash memory",

abstract = "Several memory array configurations have been proposed for single power supply flash memories. This scheme realizes 1K byte sector erasure with minimized disturbance to the unselected sectors. A memory array configuration and a decoder circuits for the DINOR flash memory have been described. The hierarchical row decoder and the compact source line driver realize 1K byte sector erasure without increasing the decoder area. The decoder pitch has been relaxed to one driver per two word lines. Narrow threshold voltage distribution has been realized by the bit-by-bit programming control and the low threshold voltage detection circuit, which achieves high speed random access time t low Vcc .",

author = "Kobayashi, {Shi ichi} and Hiroaki Nakat and Yuichi Kunori and Takeshi Nakayama and Yoshikazu Miyawaki and Yasushi Terada and Hiroshi Onoda and Natsuo Ajika and Masahiro Hatanaka and Hirokazu Misyoshi and Tsutomu Yoshihara",

year = "1993",

language = "English",

isbn = "0780312619",

pages = "97--98",

booktitle = "1993 Symposium on VLSI Circuits Digest of Technical Papers",

publisher = "Publ by IEEE",

note = "1993 Symposium on VLSI Circuits Digest of Technical Papers ; Conference date: 19-05-1993 Through 21-05-1993",

}

TY - GEN

T1 - Memory array architecture and decoding scheme for 3V only sector erasable DINOR flash memory

AU - Kobayashi, Shi ichi

AU - Nakat, Hiroaki

AU - Kunori, Yuichi

AU - Nakayama, Takeshi

AU - Miyawaki, Yoshikazu

AU - Terada, Yasushi

AU - Onoda, Hiroshi

AU - Ajika, Natsuo

AU - Hatanaka, Masahiro

AU - Misyoshi, Hirokazu

AU - Yoshihara, Tsutomu

PY - 1993

Y1 - 1993

N2 - Several memory array configurations have been proposed for single power supply flash memories. This scheme realizes 1K byte sector erasure with minimized disturbance to the unselected sectors. A memory array configuration and a decoder circuits for the DINOR flash memory have been described. The hierarchical row decoder and the compact source line driver realize 1K byte sector erasure without increasing the decoder area. The decoder pitch has been relaxed to one driver per two word lines. Narrow threshold voltage distribution has been realized by the bit-by-bit programming control and the low threshold voltage detection circuit, which achieves high speed random access time t low Vcc .

AB - Several memory array configurations have been proposed for single power supply flash memories. This scheme realizes 1K byte sector erasure with minimized disturbance to the unselected sectors. A memory array configuration and a decoder circuits for the DINOR flash memory have been described. The hierarchical row decoder and the compact source line driver realize 1K byte sector erasure without increasing the decoder area. The decoder pitch has been relaxed to one driver per two word lines. Narrow threshold voltage distribution has been realized by the bit-by-bit programming control and the low threshold voltage detection circuit, which achieves high speed random access time t low Vcc .

UR - http://www.scopus.com/inward/record.url?scp=0027843339&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0027843339&partnerID=8YFLogxK

M3 - Conference contribution

AN - SCOPUS:0027843339

SN - 0780312619

SP - 97

EP - 98

BT - 1993 Symposium on VLSI Circuits Digest of Technical Papers

PB - Publ by IEEE

CY - Piscataway, NJ, United States

T2 - 1993 Symposium on VLSI Circuits Digest of Technical Papers

Y2 - 19 May 1993 through 21 May 1993

ER -

Memory array architecture and decoding scheme for 3V only sector erasable DINOR flash memory

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Other

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