抄録
Memory design was carried out using one-transistor gain cell on SOI. This memory design is based on a one-transistor gain cell which is smaller, less complex to make and more scalable to sub-0.1μm generations than the existing dynamic random access memory (DRAM) cells, without resorting to new materials and device structure. Transient analysis of a device simulation was also discussed to verify operation of the floating body transistor cell (FBC).
本文言語 | English |
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ページ(範囲) | 152-153+454+151 |
ジャーナル | Digest of Technical Papers - IEEE International Solid-State Circuits Conference |
出版ステータス | Published - 2002 1月 1 |
外部発表 | はい |
イベント | 2002 IEEE International Solid-State Circuits Conference - San Francisco, CA, United States 継続期間: 2002 2月 3 → 2002 2月 7 |
ASJC Scopus subject areas
- 電子材料、光学材料、および磁性材料
- 電子工学および電気工学