Memory-efficient accelerating schedule for LDPC decoder

Kazunori Shimizu; Nozomu Togawa; Takeshi Ikenaga; Satoshi Goto

doi:10.1109/APCCAS.2006.342426

Memory-efficient accelerating schedule for LDPC decoder

Kazunori Shimizu^*, Nozomu Togawa, Takeshi Ikenaga, Satoshi Goto

^*この研究の対応する著者

研究成果: Conference contribution

抄録

This paper proposes a memory-efficient accelerating schedule for LDPC decoder. Important properties of the proposed techniques are as follows: (i) Partitioning a pipelined operation not to read and write intermediate messages simultaneously enables the accelerated message-passing schedule to be implemented with single-port memories. (ii) FIFO-based buffering reduces the number of memory banks and words for the decoder based on the accelerated message-passing schedule. The proposed decoder reduces the memories for intermediate messages by half compared to the conventional one based on the accelerated message-passing schedule.

本文言語	English
ホスト出版物のタイトル	APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems
ページ	1317-1320
ページ数	4
DOI	https://doi.org/10.1109/APCCAS.2006.342426
出版ステータス	Published - 2006 12月 1
イベント	APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems - , Singapore 継続期間: 2006 12月 4 → 2006 12月 6

出版物シリーズ

名前	IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS

Conference

Conference	APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems
国/地域	Singapore
Period	06/12/4 → 06/12/6

ASJC Scopus subject areas

電子工学および電気工学

文献へのアクセス

10.1109/APCCAS.2006.342426

他のファイルとリンク

引用スタイル

Shimizu, K, Togawa, N , Ikenaga, T & Goto, S 2006, Memory-efficient accelerating schedule for LDPC decoder. in APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems., 4145643, IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS, pp. 1317-1320, APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems, Singapore, 06/12/4. https://doi.org/10.1109/APCCAS.2006.342426

@inproceedings{548ef13c79c54834a0b11c7038660869,

title = "Memory-efficient accelerating schedule for LDPC decoder",

abstract = "This paper proposes a memory-efficient accelerating schedule for LDPC decoder. Important properties of the proposed techniques are as follows: (i) Partitioning a pipelined operation not to read and write intermediate messages simultaneously enables the accelerated message-passing schedule to be implemented with single-port memories. (ii) FIFO-based buffering reduces the number of memory banks and words for the decoder based on the accelerated message-passing schedule. The proposed decoder reduces the memories for intermediate messages by half compared to the conventional one based on the accelerated message-passing schedule.",

keywords = "FIFO buffer, FPGA, Low-density parity-check codes, Message-passing algorithm",

author = "Kazunori Shimizu and Nozomu Togawa and Takeshi Ikenaga and Satoshi Goto",

year = "2006",

month = dec,

day = "1",

doi = "10.1109/APCCAS.2006.342426",

language = "English",

isbn = "1424403871",

series = "IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS",

pages = "1317--1320",

booktitle = "APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems",

note = "APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems ; Conference date: 04-12-2006 Through 06-12-2006",

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T1 - Memory-efficient accelerating schedule for LDPC decoder

AU - Shimizu, Kazunori

AU - Togawa, Nozomu

AU - Ikenaga, Takeshi

AU - Goto, Satoshi

PY - 2006/12/1

Y1 - 2006/12/1

N2 - This paper proposes a memory-efficient accelerating schedule for LDPC decoder. Important properties of the proposed techniques are as follows: (i) Partitioning a pipelined operation not to read and write intermediate messages simultaneously enables the accelerated message-passing schedule to be implemented with single-port memories. (ii) FIFO-based buffering reduces the number of memory banks and words for the decoder based on the accelerated message-passing schedule. The proposed decoder reduces the memories for intermediate messages by half compared to the conventional one based on the accelerated message-passing schedule.

AB - This paper proposes a memory-efficient accelerating schedule for LDPC decoder. Important properties of the proposed techniques are as follows: (i) Partitioning a pipelined operation not to read and write intermediate messages simultaneously enables the accelerated message-passing schedule to be implemented with single-port memories. (ii) FIFO-based buffering reduces the number of memory banks and words for the decoder based on the accelerated message-passing schedule. The proposed decoder reduces the memories for intermediate messages by half compared to the conventional one based on the accelerated message-passing schedule.

KW - FIFO buffer

KW - FPGA

KW - Low-density parity-check codes

KW - Message-passing algorithm

UR - http://www.scopus.com/inward/record.url?scp=50249146836&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=50249146836&partnerID=8YFLogxK

U2 - 10.1109/APCCAS.2006.342426

DO - 10.1109/APCCAS.2006.342426

M3 - Conference contribution

AN - SCOPUS:50249146836

SN - 1424403871

SN - 9781424403875

T3 - IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS

SP - 1317

EP - 1320

BT - APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems

T2 - APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems

Y2 - 4 December 2006 through 6 December 2006

ER -

Memory-efficient accelerating schedule for LDPC decoder

抄録

出版物シリーズ

Conference

ASJC Scopus subject areas

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