We present a method for acceleration of logic simulations. The logic simulation is mainly used to detect malfunctions in the logical design phase. As the size of logical circuits grows, acceleration of the logic simulation becomes increasingly required. Several acceleration methods have been presented for this purpose. The outstanding feature of our method is that it accelerates the simulation speed in accordance with the dynamic behaviours of target circuits. A global dynamic behaviour is predicted to realize this feature, through the investigation of the relationship among gates in the early stage of the simulation. Using the relationships, a logic simulation is accelerated by a process called 'grouping'. We have confirmed that the dynamic information of the circuits accelerates logical simulation by the evaluation system.
|出版ステータス||Published - 1995 1月 1|
|イベント||Proceedings of the 1994 IEEE Region 10's 9th Annual International Conference (TENCON'94). Part 1 (of 2) - Singapore, Singapore|
継続期間: 1994 8月 22 → 1994 8月 26
|Other||Proceedings of the 1994 IEEE Region 10's 9th Annual International Conference (TENCON'94). Part 1 (of 2)|
|Period||94/8/22 → 94/8/26|
ASJC Scopus subject areas
- コンピュータ サイエンスの応用