TY - GEN
T1 - Multi-Objective Design Optimization of Power Module Performances
AU - Nakamura, Aiki
AU - Yoshida, Makoto
AU - Miyashita, Tomoyuki
N1 - Funding Information:
ACKNOWLEDGMENT This work was supported by Council for Science, Technology and Innovation (CSTI), Cross-ministerial Strategic Innovation Promotion Program (SIP), “Energy systems of an Internet of Energy (IoE) society” (JST).
Publisher Copyright:
© 2022 Japan Institute of Electronics Packaging.
PY - 2022
Y1 - 2022
N2 - As next-generation power modules develop with three-dimensional wiring structures and high-speed switching schemes, strategies to reduce the parasitic inductance and temperature will be essential to meet the increasingly demanding workloads. In this study, we developed a multi-objective design optimization system for power modules and rendered Pareto solutions outlining the inductance of the path between the main terminals, the total inductance of the paths between the control terminals, and the surface temperature of the path between the main terminals, being useful to design power modules with utmost thermal and inductance performance.
AB - As next-generation power modules develop with three-dimensional wiring structures and high-speed switching schemes, strategies to reduce the parasitic inductance and temperature will be essential to meet the increasingly demanding workloads. In this study, we developed a multi-objective design optimization system for power modules and rendered Pareto solutions outlining the inductance of the path between the main terminals, the total inductance of the paths between the control terminals, and the surface temperature of the path between the main terminals, being useful to design power modules with utmost thermal and inductance performance.
KW - inductance
KW - multi-objective design optimization
KW - power module
KW - switching loss
KW - temperature
UR - http://www.scopus.com/inward/record.url?scp=85133336700&partnerID=8YFLogxK
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U2 - 10.23919/ICEP55381.2022.9795531
DO - 10.23919/ICEP55381.2022.9795531
M3 - Conference contribution
AN - SCOPUS:85133336700
T3 - 2022 International Conference on Electronics Packaging, ICEP 2022
SP - 157
EP - 158
BT - 2022 International Conference on Electronics Packaging, ICEP 2022
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 21st International Conference on Electronics Packaging, ICEP 2022
Y2 - 11 May 2022 through 14 May 2022
ER -