Multi-stage power gating based on controlling values of logic gates

Yu Jin*, Shinji Kimura

*この研究の対応する著者

研究成果: Conference contribution

抄録

As the CMOS technology scales down, low power technologies have been expected to reduce leakage power of the CMOS device. Controlling value based power gating is a fine-grained active mode power gating approach using the controlling values of logic elements. In this method, one input of a logic gate taking the controlling value stops the power supply to the logic blocks generating other inputs. In this paper, we propose a multi-stage power gating method based on controlling values by stopping the power supply of several gates in the power controlled blocks. Experimental results show that the proposed approach increases the number of power-off elements by 26.7% in average compared with the single-stage power-gating method.

本文言語English
ホスト出版物のタイトルProceedings - 2011 IEEE 9th International Conference on ASIC, ASICON 2011
ページ79-82
ページ数4
DOI
出版ステータスPublished - 2011 12月 1
イベント2011 IEEE 9th International Conference on ASIC, ASICON 2011 - Xiamen, China
継続期間: 2011 10月 252011 10月 28

出版物シリーズ

名前Proceedings of International Conference on ASIC
ISSN(印刷版)2162-7541
ISSN(電子版)2162-755X

Conference

Conference2011 IEEE 9th International Conference on ASIC, ASICON 2011
国/地域China
CityXiamen
Period11/10/2511/10/28

ASJC Scopus subject areas

  • ハードウェアとアーキテクチャ
  • 電子工学および電気工学

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