抄録
A CR-delay circuit technology for the realization of high-speed operation with a wide operational margin and minimized timing loss is discussed. It was applied to a 4-Mb CMOS DRAM, and the experimental results are described. A significant reduction in access time and cycle time was achieved.
| 本文言語 | English |
|---|---|
| ページ | 75-76 |
| ページ数 | 2 |
| 出版ステータス | Published - 1988 12月 1 |
| 外部発表 | はい |
| イベント | 1988 Symposium on VLSI Circuits - Digest of Technical Papers - Tokyo, Japan 継続期間: 1988 8月 22 → 1988 8月 24 |
Other
| Other | 1988 Symposium on VLSI Circuits - Digest of Technical Papers |
|---|---|
| City | Tokyo, Japan |
| Period | 88/8/22 → 88/8/24 |
ASJC Scopus subject areas
- 工学（全般）