A CR-delay circuit technology for the realization of high-speed operation with a wide operational margin and minimized timing loss is discussed. It was applied to a 4-Mb CMOS DRAM, and the experimental results are described. A significant reduction in access time and cycle time was achieved.
|出版ステータス||Published - 1988 12月 1|
|イベント||1988 Symposium on VLSI Circuits - Digest of Technical Papers - Tokyo, Japan|
継続期間: 1988 8月 22 → 1988 8月 24
|Other||1988 Symposium on VLSI Circuits - Digest of Technical Papers|
|Period||88/8/22 → 88/8/24|
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