The paper presents a new design method for custom LSI layouts. This method is based on layout compaction with automatic jog (wiring bend) generation in the layout. A dense chip design can be realized by this technique. Experimental results show that the chip size, designed by using the proposed layout method, is only 1. 2 to approx 1. 4 times larger than that resulting from manual layouts. Therefore, this compaction-based custom LSI layout design method is very effective in achieving a minimal chip layout design.
|ジャーナル||NEC Research and Development|
|出版ステータス||Published - 1988 4月|
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