New power-aware placement for region-based FPGA architecture combined with dynamic power gating by PCHM

Ce Li*, Yiping Dong, Takahiro Watanabe

*この研究の対応する著者

研究成果: Conference contribution

10 被引用数 (Scopus)

抄録

The power consumption of FPGA is larger than that of ASIC to perform the same function in the same scaling. In this paper, we propose a Power Control Hard Macro (PCHM) based coarse-grained power gating FPGA architecture to dynamically reduce the power consumption. The algorithm of the placement based on sleep region is presented. After enhancing the CAD framework, a detailed study is given under different region size supported by the new FPGA architecture. As a result, the proposed architecture and the placement algorithm can reduce 51% power consumption on average compared with normal architecture.

本文言語English
ホスト出版物のタイトルIEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2011
ページ223-228
ページ数6
DOI
出版ステータスPublished - 2011 9月 19
イベント17th IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2011 - Fukuoka, Japan
継続期間: 2011 8月 12011 8月 3

出版物シリーズ

名前Proceedings of the International Symposium on Low Power Electronics and Design
ISSN(印刷版)1533-4678

Other

Other17th IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2011
国/地域Japan
CityFukuoka
Period11/8/111/8/3

ASJC Scopus subject areas

  • 工学(全般)

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