Optimized design for high-performance megabit DRAMs

Masaki Kumanoya; Katsumi Dosaka; Yashuhiro Konishi; Tsutomu Yoshihara; Hideshi Miyatake; Yuto Ikeda; Isao Furuta

Optimized design for high-performance megabit DRAMs

Masaki Kumanoya^*, Katsumi Dosaka, Yashuhiro Konishi, Tsutomu Yoshihara, Hideshi Miyatake, Yuto Ikeda, Isao Furuta

^*この研究の対応する著者

研究成果: Article › 査読

1 被引用数 (Scopus)

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Actual guidelines for the techniques to be employed for high-performance megabit DRAMs have been studied based on the performance analysis of conventional NMOS 1MDRAMs. The design technology to be employed for effective use of these new process techniques has been analyzed and optimized. CMOS 1MDRAMs were fabricated. The RAS access time at 5 V and 25°C was 50 ns with the current consumption of 28 mA (t_c = 260 ns). Since the average standby current at a refresh interval of 64 ms was 80 μA, battery backup is possible in this high-performance 1MDRAM.

本文言語	English
ページ（範囲）	14-23
ページ数	10
ジャーナル	Electronics and Communications in Japan, Part II: Electronics (English translation of Denshi Tsushin Gakkai Ronbunshi)
巻	72
号	8
出版ステータス	Published - 1989 8月
外部発表	はい

ASJC Scopus subject areas

電子工学および電気工学

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@article{7eae08715fa041c49be89d73555824ee,

title = "Optimized design for high-performance megabit DRAMs",

abstract = "Actual guidelines for the techniques to be employed for high-performance megabit DRAMs have been studied based on the performance analysis of conventional NMOS 1MDRAMs. The design technology to be employed for effective use of these new process techniques has been analyzed and optimized. CMOS 1MDRAMs were fabricated. The RAS access time at 5 V and 25°C was 50 ns with the current consumption of 28 mA (tc = 260 ns). Since the average standby current at a refresh interval of 64 ms was 80 μA, battery backup is possible in this high-performance 1MDRAM.",

author = "Masaki Kumanoya and Katsumi Dosaka and Yashuhiro Konishi and Tsutomu Yoshihara and Hideshi Miyatake and Yuto Ikeda and Isao Furuta",

year = "1989",

month = aug,

language = "English",

volume = "72",

pages = "14--23",

journal = "Electronics and Communications in Japan, Part II: Electronics (English translation of Denshi Tsushin Gakkai Ronbunshi)",

issn = "8756-663X",

publisher = "Scripta Technica",

number = "8",

}

TY - JOUR

T1 - Optimized design for high-performance megabit DRAMs

AU - Kumanoya, Masaki

AU - Dosaka, Katsumi

AU - Konishi, Yashuhiro

AU - Yoshihara, Tsutomu

AU - Miyatake, Hideshi

AU - Ikeda, Yuto

AU - Furuta, Isao

PY - 1989/8

Y1 - 1989/8

N2 - Actual guidelines for the techniques to be employed for high-performance megabit DRAMs have been studied based on the performance analysis of conventional NMOS 1MDRAMs. The design technology to be employed for effective use of these new process techniques has been analyzed and optimized. CMOS 1MDRAMs were fabricated. The RAS access time at 5 V and 25°C was 50 ns with the current consumption of 28 mA (tc = 260 ns). Since the average standby current at a refresh interval of 64 ms was 80 μA, battery backup is possible in this high-performance 1MDRAM.

AB - Actual guidelines for the techniques to be employed for high-performance megabit DRAMs have been studied based on the performance analysis of conventional NMOS 1MDRAMs. The design technology to be employed for effective use of these new process techniques has been analyzed and optimized. CMOS 1MDRAMs were fabricated. The RAS access time at 5 V and 25°C was 50 ns with the current consumption of 28 mA (tc = 260 ns). Since the average standby current at a refresh interval of 64 ms was 80 μA, battery backup is possible in this high-performance 1MDRAM.

UR - http://www.scopus.com/inward/record.url?scp=0024717756&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0024717756&partnerID=8YFLogxK

M3 - Article

AN - SCOPUS:0024717756

SN - 8756-663X

VL - 72

SP - 14

EP - 23

JO - Electronics and Communications in Japan, Part II: Electronics (English translation of Denshi Tsushin Gakkai Ronbunshi)

JF - Electronics and Communications in Japan, Part II: Electronics (English translation of Denshi Tsushin Gakkai Ronbunshi)

IS - 8

ER -

Optimized design for high-performance megabit DRAMs

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