Parallel architecture for high-speed Reed-Solomon codec

T. K. Matsushima, T. Matsushima, S. Hirasawa

研究成果: Conference contribution

14 被引用数 (Scopus)


This paper presents a parallel architecture for a high-speed Reed-Solomon (RS) encoder and decoder (codec) LSI. Since the architecture allows H symbols to be processed in parallel the codec LSI achieves a data rate of mLH b/s. where m is the symbol size (m bits per symbol), L is the clock frequency of the circuit, and H is an arbitrary integer. As an example, we investigate hardware complexity, delay and critical path length for a (255.251) RS code. It is shown that both the hardware complexity and the delay for a parallel circuit is much less than that with the parallel operation of H conventional circuits. Although the only problem with, this parallel architecture is that the encoder's critical path length increases with H, the proposed architectures is more efficient than a setup using H conventional circuits for high data rate applications. It is also suggested that parallel RS codecs, which can keep up with optical transmission rates, i.e. several giga bits/sec. could be implemented on one LSI chip, using current CMOS technology.

ホスト出版物のタイトルITS 1998 Proceedings - SBT/IEEE International Telecommunications Symposium
出版社Institute of Electrical and Electronics Engineers Inc.
ISBN(電子版)0780350308, 9780780350304
出版ステータスPublished - 1998
イベントSBT/IEEE International Telecommunications Symposium, ITS 1998 - Sao Paulo, Brazil
継続期間: 1998 8月 91998 8月 13


名前ITS 1998 Proceedings - SBT/IEEE International Telecommunications Symposium


OtherSBT/IEEE International Telecommunications Symposium, ITS 1998
CitySao Paulo

ASJC Scopus subject areas

  • コンピュータ ネットワークおよび通信
  • 信号処理


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