抄録
As the development of semiconductor industry, 3D IC technology is introduced for its advantages in alleviating the interconnect problem coming with decreasing feature size and increasing integrated density. In 3D IC fabrication, one of the key challenges is the vertical connections between different device layers, which can be implemented by interlayer vias. In this paper, we proposed a performance-maximized interlayer via planning method for 3D ICs (multiple device layers), which can be used in the post-floorplanning stage.
| 本文言語 | English |
|---|---|
| ホスト出版物のタイトル | ASICON 2007 - 2007 7th International Conference on ASIC Proceeding |
| ページ | 1096-1099 |
| ページ数 | 4 |
| DOI | |
| 出版ステータス | Published - 2007 |
| イベント | 2007 7th International Conference on ASIC, ASICON 2007 - Guilin 継続期間: 2007 10月 26 → 2007 10月 29 |
Other
| Other | 2007 7th International Conference on ASIC, ASICON 2007 |
|---|---|
| City | Guilin |
| Period | 07/10/26 → 07/10/29 |
ASJC Scopus subject areas
- ハードウェアとアーキテクチャ
- 電子工学および電気工学