Pin accessibility evaluating model for improving routability of VLSI designs

Hong Yan Su, Shinichi Nishizawa, Yan Shiun Wu, Jun Shiomi, Yih Lang Li, Hidetoshi Onodera

研究成果: Conference contribution

4 被引用数 (Scopus)

抄録

Pin accessibility influences the routability of a design at the stage of block/chip assembling. The estimation model for pin accessibility in previous researches counts the total number of intersections between each pin and M2 routing tracks. It does not consider the variation of pin accessibility as the spacing between a pin and its neighboring pins and metal wires changes. Besides, it cannot properly deal with the off-grid pin access neither. In this paper, we propose a general model for pin accessibility estimation. In the model, all directions to connect to the boundary of a pin are under estimation. Off-grid pin access is also available. Experimental results show that the reduction rate of minimum area to complete the routing of a circuit can be 7.0% on average. Due to the diminishment of required area for routing, the total number of vias for higher metal layer also decrease under the same area constraint.

本文言語English
ホスト出版物のタイトルProceedings - 30th IEEE International System on Chip Conference, SOCC 2017
編集者Jurgen Becker, Ramalingam Sridhar, Hai Li, Ulf Schlichtmann, Massimo Alioto
出版社IEEE Computer Society
ページ56-61
ページ数6
ISBN(電子版)9781538640333
DOI
出版ステータスPublished - 2017 12月 18
外部発表はい
イベント30th IEEE International System on Chip Conference, SOCC 2017 - Munich, Germany
継続期間: 2017 9月 52017 9月 8

出版物シリーズ

名前International System on Chip Conference
2017-September
ISSN(印刷版)2164-1676
ISSN(電子版)2164-1706

Conference

Conference30th IEEE International System on Chip Conference, SOCC 2017
国/地域Germany
CityMunich
Period17/9/517/9/8

ASJC Scopus subject areas

  • ハードウェアとアーキテクチャ
  • 制御およびシステム工学
  • 電子工学および電気工学

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