抄録
This paper develops pipeline architecture of particle swarm optimization with random time-varying inertia weight and acceleration coefficients (PSO-RTVIWAC) based on existing serial architecture. The proposed architecture incorporated two features to reduce calculation error and keep high speed calculation with acceptable chip area cost. First, actual hardware design is simplified. Then the pipeline mechanism is introduced. The developed system is implemented in field programmable gate array (FPGA) and achieves high stability with slightly increased speed.
本文言語 | English |
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ホスト出版物のタイトル | Proceedings - 9th IEEE/ACIS International Conference on Computer and Information Science, ICIS 2010 |
ページ | 3-8 |
ページ数 | 6 |
DOI | |
出版ステータス | Published - 2010 |
イベント | 9th IEEE/ACIS International Conference on Computer and Information Science, ICIS 2010 - Yamagata 継続期間: 2010 8月 18 → 2010 8月 20 |
Other
Other | 9th IEEE/ACIS International Conference on Computer and Information Science, ICIS 2010 |
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City | Yamagata |
Period | 10/8/18 → 10/8/20 |
ASJC Scopus subject areas
- 情報システム