Power-aware compiler controllable chip multiprocessor

Hiroaki Shikano; Jun Shirako; Yasutaka Wada; Keiji Kimura; Hironori Kasahara

doi:10.1109/PACT.2007.4336255

Power-aware compiler controllable chip multiprocessor

Hiroaki Shikano^*, Jun Shirako, Yasutaka Wada, Keiji Kimura, Hironori Kasahara

^*この研究の対応する著者

基幹理工学部

研究成果: Conference contribution

1 被引用数 (Scopus)

本文言語	English
ホスト出版物のタイトル	16th International Conference on Parallel Architecture and Compilation Techniques, PACT 2007
ページ数	1
DOI	https://doi.org/10.1109/PACT.2007.4336255
出版ステータス	Published - 2007 12月 1
イベント	16th International Conference on Parallel Architecture and Compilation Techniques, PACT 2007 - Brasov, Romania 継続期間: 2007 9月 15 → 2007 9月 19

出版物シリーズ

名前	Parallel Architectures and Compilation Techniques - Conference Proceedings, PACT
ISSN（印刷版）	1089-795X

Conference

Conference	16th International Conference on Parallel Architecture and Compilation Techniques, PACT 2007
国/地域	Romania
City	Brasov
Period	07/9/15 → 07/9/19

ASJC Scopus subject areas

ソフトウェア
理論的コンピュータサイエンス
ハードウェアとアーキテクチャ

文献へのアクセス

10.1109/PACT.2007.4336255

他のファイルとリンク

引用スタイル

Shikano, H, Shirako, J, Wada, Y, Kimura, K & Kasahara, H 2007, Power-aware compiler controllable chip multiprocessor. in 16th International Conference on Parallel Architecture and Compilation Techniques, PACT 2007., 4336255, Parallel Architectures and Compilation Techniques - Conference Proceedings, PACT, 16th International Conference on Parallel Architecture and Compilation Techniques, PACT 2007, Brasov, Romania, 07/9/15. https://doi.org/10.1109/PACT.2007.4336255

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