PRACTICAL STUDY ON THE ARCHITECTURE OF VLSI DSP.

The architecture of a pipelined multiplier is examined. The throughput of a 16-bit multiplier using fixed-point arithmetic is analyzed for a single-cycle structure, a 2-stage pipeline structure, and a 3-stage pipeline structure. The total efficiency, which includes overheads inherent to a pipeline structure, is examined for each structure for programs developed for practical applications such as a 32 kb/s SDPCM codec, an echo canceller, 19-section filter banks for voice recognition, etc. Each analysis showed that the 2-stage pipeline structure is a suitable choice from the viewpoints of efficiency and simplicity of programming.