TY - GEN
T1 - Precise timing verification of logic circuits under combined delay model
AU - Kimura, Shinji
AU - Kashima, Shigemi
AU - Haneda, Hiromasa
PY - 1992/1/1
Y1 - 1992/1/1
N2 - The paper proposes a combined delay model to manipulate the variance of the delay time of logic elements and a new timing verification method based on the theory of regular expressions. We focused on the hazard detection problem and the verification of asynchronous circuits, and show the effectiveness of our method with medium sized circuits including 100 elements or so.
AB - The paper proposes a combined delay model to manipulate the variance of the delay time of logic elements and a new timing verification method based on the theory of regular expressions. We focused on the hazard detection problem and the verification of asynchronous circuits, and show the effectiveness of our method with medium sized circuits including 100 elements or so.
UR - http://www.scopus.com/inward/record.url?scp=0026965950&partnerID=8YFLogxK
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U2 - 10.1109/iccad.1992.279317
DO - 10.1109/iccad.1992.279317
M3 - Conference contribution
AN - SCOPUS:0026965950
SN - 0818630108
SN - 9780818630101
T3 - IEEE/ACM International Conference on Computer-Aided Design
SP - 526
EP - 529
BT - IEEE/ACM International Conference on Computer-Aided Design
PB - Publ by IEEE
T2 - IEEE/ACM International Conference on Computer-Aided Design - ICCAD '92
Y2 - 8 November 1992 through 12 November 1992
ER -