## 抄録

The discrete time analysis of logic circuits is usually more efficient than the continuous time analysis, but the preciseness of the discrete time analysis is not guaranteed. The paper shows a method to decide a unit time for a logic circuit under which the analysis result is the same as the result based on the continuous time. The delay time of an element is specified with an interval between the minimum and maximum delay times, and we assume an analysis method which enumerates all possible delay cases under the discrete time. Our main theorem is as follows: refine the unit time by a factor of 1/2, and if the analysis result with a unit time u and that with a unit time u/2 are the same, then us is the expected unit time.

本文言語 | English |
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ページ（範囲） | 1755-1756 |

ページ数 | 2 |

ジャーナル | IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences |

巻 | E76-A |

号 | 10 |

出版ステータス | Published - 1993 10月 1 |

外部発表 | はい |

## ASJC Scopus subject areas

- 信号処理
- コンピュータ グラフィックスおよびコンピュータ支援設計
- 電子工学および電気工学
- 応用数学