Reconfigurable adaptive FEC system with interleaving

Kazunori Shimizu; Nozomu Togawa; Takeshi Ikenaga; Satoshi Goto

Reconfigurable adaptive FEC system with interleaving

Kazunori Shimizu^*, Nozomu Togawa, Takeshi Ikenaga, Satoshi Goto

^*この研究の対応する著者

研究成果: Conference contribution

抄録

This paper proposes a reconfigurable adaptive FEC system with interleaving. For adaptive FEC schemes, we can implement an optimal RS decoder composed of minimum hardware units for any given error correction capability t. If the hardware units of the RS decoder can be reduced for any given t, we can embed as large deinterleaver as possible into the RS decoder for each t. Reconfiguring the RS decoder embedded with the expanded deinterleaver dynamically for each t allows us to decode larger interleaved codes which are more robust FEC codes to burst errors. Our reconfigurable adaptive FEC system with interleaving achieves better packet error rate and higher throughput than fixed hardware systems.

本文言語	English
ホスト出版物のタイトル	Proceedings of the 2005 Asia and South Pacific Design Automation Conference, ASP-DAC 2005
ページ	1252-1255
ページ数	4
出版ステータス	Published - 2005 12月 1
イベント	2005 Asia and South Pacific Design Automation Conference, ASP-DAC 2005 - Shanghai, China 継続期間: 2005 1月 18 → 2005 1月 21

出版物シリーズ

名前	Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
巻	2

Conference

Conference	2005 Asia and South Pacific Design Automation Conference, ASP-DAC 2005
国/地域	China
City	Shanghai
Period	05/1/18 → 05/1/21

ASJC Scopus subject areas

コンピュータサイエンスの応用
コンピュータグラフィックスおよびコンピュータ支援設計
電子工学および電気工学

他のファイルとリンク

引用スタイル

Shimizu, K, Togawa, N , Ikenaga, T & Goto, S 2005, Reconfigurable adaptive FEC system with interleaving. in Proceedings of the 2005 Asia and South Pacific Design Automation Conference, ASP-DAC 2005., 1466570, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, vol. 2, pp. 1252-1255, 2005 Asia and South Pacific Design Automation Conference, ASP-DAC 2005, Shanghai, China, 05/1/18.

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AU - Ikenaga, Takeshi

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Y1 - 2005/12/1

N2 - This paper proposes a reconfigurable adaptive FEC system with interleaving. For adaptive FEC schemes, we can implement an optimal RS decoder composed of minimum hardware units for any given error correction capability t. If the hardware units of the RS decoder can be reduced for any given t, we can embed as large deinterleaver as possible into the RS decoder for each t. Reconfiguring the RS decoder embedded with the expanded deinterleaver dynamically for each t allows us to decode larger interleaved codes which are more robust FEC codes to burst errors. Our reconfigurable adaptive FEC system with interleaving achieves better packet error rate and higher throughput than fixed hardware systems.

AB - This paper proposes a reconfigurable adaptive FEC system with interleaving. For adaptive FEC schemes, we can implement an optimal RS decoder composed of minimum hardware units for any given error correction capability t. If the hardware units of the RS decoder can be reduced for any given t, we can embed as large deinterleaver as possible into the RS decoder for each t. Reconfiguring the RS decoder embedded with the expanded deinterleaver dynamically for each t allows us to decode larger interleaved codes which are more robust FEC codes to burst errors. Our reconfigurable adaptive FEC system with interleaving achieves better packet error rate and higher throughput than fixed hardware systems.

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M3 - Conference contribution

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T3 - Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

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BT - Proceedings of the 2005 Asia and South Pacific Design Automation Conference, ASP-DAC 2005

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Reconfigurable adaptive FEC system with interleaving

抄録

出版物シリーズ

Conference

ASJC Scopus subject areas

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