TY - JOUR
T1 - Reconfigurable circuit design based on arithmetic logic unit using double-gate cntfets
AU - Ninomiya, Hiroshi
AU - Kobayashi, Manabu
AU - Miura, Yasuyuki
AU - Watanabe, Shigeyoshi
PY - 2014
Y1 - 2014
N2 - This letter describes a design methodology for an arithmetic logic unit (ALU) incorporating reconfigurability based on doublegate carbon nanotube field-effect transistors (DG-CNTFETs). The design of a DG-CNTFET with an ambipolar-property-based reconfigurable static logic circuit is simple and straightforward using an ambipolar binary decision diagram (Am-BDD), which represents the cornerstone for the automatic pass transistor logic (PTL) synthesis flows of ambipolar devices. In this work, an ALU with 16 functions is synthesized by the design methodology of a DG-CNTFET-based reconfigurable static logic circuit. Furthermore, it is shown that the proposed ALU is much more flexible and practical than a conventional DG-CNTFET-based reconfigurable ALU.
AB - This letter describes a design methodology for an arithmetic logic unit (ALU) incorporating reconfigurability based on doublegate carbon nanotube field-effect transistors (DG-CNTFETs). The design of a DG-CNTFET with an ambipolar-property-based reconfigurable static logic circuit is simple and straightforward using an ambipolar binary decision diagram (Am-BDD), which represents the cornerstone for the automatic pass transistor logic (PTL) synthesis flows of ambipolar devices. In this work, an ALU with 16 functions is synthesized by the design methodology of a DG-CNTFET-based reconfigurable static logic circuit. Furthermore, it is shown that the proposed ALU is much more flexible and practical than a conventional DG-CNTFET-based reconfigurable ALU.
KW - Ambipolar device
KW - Arithmetic logic unit
KW - Binary decision diagram
KW - Doublegate CNTFET
KW - Reconfigurable logic circuit design
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U2 - 10.1587/transfun.E97.A.675
DO - 10.1587/transfun.E97.A.675
M3 - Article
AN - SCOPUS:84893335087
SN - 0916-8508
VL - E97-A
SP - 675
EP - 678
JO - IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
JF - IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
IS - 2
ER -