Register allocation technique using guarded PDG

Akira Koseki*, Hideaki Komatsu, Yoshiaki Fukazawa


研究成果: Paper査読

1 被引用数 (Scopus)


Register allocation for instruction-level parallel processors involves problems that are not considered in register allocation for scalar processors. First, when the same register is allocated to different variables, anti-dependence is generated, which decreases instruction-level parallelism. Second, spill code should be inserted at a suitable position in its object, where it can be executed in parallel with other instructions. These problems do not exist for scalar processors, so existing register allocators take no account of them. This paper describes a new register allocation algorithm for solving these problems, using a graph structure that represents instructions and dependences between them.

出版ステータスPublished - 1996
イベントProceedings of the 1996 International Conference on Supercomputing - Philadelphia, PA, USA
継続期間: 1996 5月 251996 5月 28


OtherProceedings of the 1996 International Conference on Supercomputing
CityPhiladelphia, PA, USA

ASJC Scopus subject areas

  • コンピュータ サイエンス(全般)


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