Register length analysis and VLSI optimization of VBS hadamard transform in H.264/AVC

Fidelity range extensions of H.264/AVC adopt variable block size (VBS) transform techniques to employ 8× 8/4×4 Hadamard transforms adaptively during the fractional motion estimation. In this literature, the hardwired VBS Hadamard transform accelerator is developed with the following contributions: 1) developed a hardware reusing scheme between 8×8 and 4×4 transforms within the architecture design; 2) devised the intermediate bit-truncation algorithm to reduce the hardware cost while maintaining the computational precision well; and 3) reduced the bit-width of sum of absolute transformed differences (SATD) value as compared to the primitive implementation, resulting in optimization in both power and hardware cost for the SATD generator implementation. With TSMC 0.18 μm CMOS technology, the experiments demonstrate that for each VBS Hadamard transform engine, 13.030.4% saving in hardware cost and 12.632.4% saving in power consumption are achieved, whereas the incurred coding quality loss is less than 0.2089 dB in terms of BDPSNR. From the aspect of the whole encoder implementation, and considering the parallelism in searching factional pixel candidates, the proposed strategies garner 2.03.9% overall gate count reduction.