TY - GEN
T1 - Reliability Assessment and Quantitative Evaluation of Soft-Error Resilient 3D Network-on-Chip Systems
AU - Dang, Khanh N.
AU - Meyer, Michael
AU - Okuyama, Yuichi
AU - Abdallah, Abderazek Ben
N1 - Publisher Copyright:
© 2016 IEEE.
PY - 2016/12/22
Y1 - 2016/12/22
N2 - Three-Dimensional Networks-on-Chips (3D-NoCs) have been proposed as an auspicious solution, merging the high parallelism of the Network-on-Chip (NoC) paradigm with the high-performance and low-power cost of 3D-ICs. However, as technology scales down, the reliability issues are becoming more crucial, especially for complex 3D-NoC which provides the communication requirements of multi and many-core systems-on-chip. Reliability assessment is prominent for early stages of the manufacturing process to prevent costly redesigns of a target system. In this paper, we present an accurate reliability assessment and quantitative evaluation of a soft-error resilient 3D-NoC based on a soft-error resilient mechanism. The system can recover from transient errors occurring in different pipeline stages of the router. Based on this analysis, the effects of failures in the network's principal components are determined.
AB - Three-Dimensional Networks-on-Chips (3D-NoCs) have been proposed as an auspicious solution, merging the high parallelism of the Network-on-Chip (NoC) paradigm with the high-performance and low-power cost of 3D-ICs. However, as technology scales down, the reliability issues are becoming more crucial, especially for complex 3D-NoC which provides the communication requirements of multi and many-core systems-on-chip. Reliability assessment is prominent for early stages of the manufacturing process to prevent costly redesigns of a target system. In this paper, we present an accurate reliability assessment and quantitative evaluation of a soft-error resilient 3D-NoC based on a soft-error resilient mechanism. The system can recover from transient errors occurring in different pipeline stages of the router. Based on this analysis, the effects of failures in the network's principal components are determined.
KW - 3D Network-on-Chip
KW - Architecture
KW - Fault-tolerant
KW - Reliability Assessment
KW - Soft-Error
UR - http://www.scopus.com/inward/record.url?scp=85010197282&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85010197282&partnerID=8YFLogxK
U2 - 10.1109/ATS.2016.37
DO - 10.1109/ATS.2016.37
M3 - Conference contribution
AN - SCOPUS:85010197282
T3 - Proceedings of the Asian Test Symposium
SP - 161
EP - 166
BT - Proceedings - 2016 IEEE 25th Asian Test Symposium, ATS 2016
PB - IEEE Computer Society
T2 - 25th IEEE Asian Test Symposium, ATS 2016
Y2 - 21 November 2016 through 24 November 2016
ER -