Remapping method to minimize makespan of simulink model for embedded multi-core systems

Sasuga Kojima, Masato Edahiro, Takuya Azumi

研究成果: Conference contribution

5 被引用数 (Scopus)

抄録

Multi-core processors have been increasingly used to reduce power consumption and improve performance in embedded systems. In addition, a use of Model-Based Development has been increasing. Relative to these trends, Model-Based Parallelizer (MBP) has an essential role in parallelizing applications (i.e., Simulink blocks). MBP maps Simulink blocks to cores at the model level using various information. Generally, mapping blocks to cores is considered an NP-hard graph optimization problem; thus, MBP uses a heuristic method to solve it. A heuristic method can solve problems at high speed, but it is often not accurate. Therefore, this paper proposes two methods to improve results of MBP. The first method remaps blocks to cores based on the results of MBP. The second method determines an execution order that can finish the entire process faster than existing methods. Evaluations demonstrate that the proposed methods can obtain better results than existing methods in terms of Speedup and Load-Balancing.

本文言語English
ホスト出版物のタイトルProceedings of the 33rd International Conference on Computers and Their Applications, CATA 2018
編集者Gordon Lee, Les Miller
出版社The International Society for Computers and Their Applications (ISCA)
ISBN(電子版)9781943436101
出版ステータスPublished - 2018
イベント33rd International Conference on Computers and Their Applications, CATA 2018 - Las Vegas, United States
継続期間: 2018 3月 192018 3月 21

出版物シリーズ

名前Proceedings of the 33rd International Conference on Computers and Their Applications, CATA 2018
2018-March

Conference

Conference33rd International Conference on Computers and Their Applications, CATA 2018
国/地域United States
CityLas Vegas
Period18/3/1918/3/21

ASJC Scopus subject areas

  • コンピュータ サイエンスの応用

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