TY - GEN
T1 - Robust AES circuit design for delay variation using suspicious timing error prediction
AU - Yahagi, Yuki
AU - Yanagisawa, Masao
AU - Togawa, Nozomu
N1 - Publisher Copyright:
© 2017 IEEE.
PY - 2018/5/29
Y1 - 2018/5/29
N2 - This paper proposes a robust AES (advanced encryption standard) circuit for delay variation. In our proposed AES circuit, suspicious timing error prediction circuits (STEPCs) and their associating gating circuit are incorporated into a normal AES circuit to predict timing errors. STEPCs are inserted between inter-module connections and thus we can monitor almost all of the signal paths between registers and effectively prevent timing errors. The simulation results demonstrate that our AES circuit with STEPCs can be overclocked by up to 1.66X with just 8.05% area overheads.
AB - This paper proposes a robust AES (advanced encryption standard) circuit for delay variation. In our proposed AES circuit, suspicious timing error prediction circuits (STEPCs) and their associating gating circuit are incorporated into a normal AES circuit to predict timing errors. STEPCs are inserted between inter-module connections and thus we can monitor almost all of the signal paths between registers and effectively prevent timing errors. The simulation results demonstrate that our AES circuit with STEPCs can be overclocked by up to 1.66X with just 8.05% area overheads.
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U2 - 10.1109/ISOCC.2017.8368789
DO - 10.1109/ISOCC.2017.8368789
M3 - Conference contribution
AN - SCOPUS:85048887213
T3 - Proceedings - International SoC Design Conference 2017, ISOCC 2017
SP - 101
EP - 102
BT - Proceedings - International SoC Design Conference 2017, ISOCC 2017
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 14th International SoC Design Conference, ISOCC 2017
Y2 - 5 November 2017 through 8 November 2017
ER -