抄録
Scan technology carries the potential risk of being misused as a side channel to leak out the secrets of crypto cores. The existing scan-based attacks could be viewed as one kind of differential cryptanalysis, which takes advantages of scan chains to observe the bit changes between pairs of chosen plaintexts so as to identify the secret keys. To address such a design/test challenge, this paper proposes a robust secure scan structure design for crypto cores as a countermeasure against scan-based attacks to maintain high security without compromising the testability.
本文言語 | English |
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論文番号 | 5734887 |
ページ(範囲) | 176-181 |
ページ数 | 6 |
ジャーナル | IEEE Transactions on Very Large Scale Integration (VLSI) Systems |
巻 | 20 |
号 | 1 |
DOI | |
出版ステータス | Published - 2012 1月 |
ASJC Scopus subject areas
- ソフトウェア
- ハードウェアとアーキテクチャ
- 電子工学および電気工学