Row-redundancy scheme for high-density flash memory

Masaaki Mihara; Takeshi Nakayama; Minoru Ohkawa; Shinji Kawai; Yoshikazu Milyawaki; Yesushi Tereda; Makoto Ohi; Hiroshi Onoda; Natsuo Ajika; Masahiro Hatanaka; Hirokazu Miyoshi; Tsutomu Yoshihara

Row-redundancy scheme for high-density flash memory

Masaaki Mihara^*, Takeshi Nakayama, Minoru Ohkawa, Shinji Kawai, Yoshikazu Milyawaki, Yesushi Tereda, Makoto Ohi, Hiroshi Onoda, Natsuo Ajika, Masahiro Hatanaka, Hirokazu Miyoshi, Tsutomu Yoshihara

^*この研究の対応する著者

研究成果: Conference contribution

5 被引用数 (Scopus)

抄録

This paper describes the application of Gray code to the row decoder so that programming before erasure can be done to the defect word lines without incurring area penalty. Using this technique, a 3.3V operation 16Mb CMOS flash memory is fabricated in 0.5μm CMOS technology. The cell is 75ns at 3.3V Vcc. Process parameters and typical characteristics of the 16Mb memory are summarized. A block diagram of the chip is shown. The array is divided into 8 planes. Each plane is divided into four independently erasable 64kB blocks. There are 16 redundant WLs and 128 redundant columns. 65% of the repaired chips are confirmed by the proposed row redundancy system. Although the scheme is proven only by a limited number of devices, it apparently will be useful independent of the line level and the stage of manufacture. A micrograph of this chip is shown.

本文言語	English
ホスト出版物のタイトル	Digest of Technical Papers - IEEE International Solid-State Circuits Conference
編集者	Anon
Place of Publication	Piscataway, NJ, United States
出版社	Publ by IEEE
ページ	150-151
ページ数	2
ISBN（印刷版）	0780318455
出版ステータス	Published - 1994
外部発表	はい
イベント	Proceedings of the 1994 IEEE International Solid-State Circuits Conference - San Francisco, CA, USA 継続期間: 1994 2月 16 → 1994 2月 18

Other

Other	Proceedings of the 1994 IEEE International Solid-State Circuits Conference
City	San Francisco, CA, USA
Period	94/2/16 → 94/2/18

ASJC Scopus subject areas

ハードウェアとアーキテクチャ
電子工学および電気工学
工学（全般）

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引用スタイル

Mihara, M, Nakayama, T, Ohkawa, M, Kawai, S, Milyawaki, Y, Tereda, Y, Ohi, M, Onoda, H, Ajika, N, Hatanaka, M, Miyoshi, H & Yoshihara, T 1994, Row-redundancy scheme for high-density flash memory. in Anon (ed.), Digest of Technical Papers - IEEE International Solid-State Circuits Conference. Publ by IEEE, Piscataway, NJ, United States, pp. 150-151, Proceedings of the 1994 IEEE International Solid-State Circuits Conference, San Francisco, CA, USA, 94/2/16.

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title = "Row-redundancy scheme for high-density flash memory",

abstract = "This paper describes the application of Gray code to the row decoder so that programming before erasure can be done to the defect word lines without incurring area penalty. Using this technique, a 3.3V operation 16Mb CMOS flash memory is fabricated in 0.5μm CMOS technology. The cell is 75ns at 3.3V Vcc. Process parameters and typical characteristics of the 16Mb memory are summarized. A block diagram of the chip is shown. The array is divided into 8 planes. Each plane is divided into four independently erasable 64kB blocks. There are 16 redundant WLs and 128 redundant columns. 65% of the repaired chips are confirmed by the proposed row redundancy system. Although the scheme is proven only by a limited number of devices, it apparently will be useful independent of the line level and the stage of manufacture. A micrograph of this chip is shown.",

author = "Masaaki Mihara and Takeshi Nakayama and Minoru Ohkawa and Shinji Kawai and Yoshikazu Milyawaki and Yesushi Tereda and Makoto Ohi and Hiroshi Onoda and Natsuo Ajika and Masahiro Hatanaka and Hirokazu Miyoshi and Tsutomu Yoshihara",

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booktitle = "Digest of Technical Papers - IEEE International Solid-State Circuits Conference",

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AU - Mihara, Masaaki

AU - Nakayama, Takeshi

AU - Ohkawa, Minoru

AU - Kawai, Shinji

AU - Milyawaki, Yoshikazu

AU - Tereda, Yesushi

AU - Ohi, Makoto

AU - Onoda, Hiroshi

AU - Ajika, Natsuo

AU - Hatanaka, Masahiro

AU - Miyoshi, Hirokazu

AU - Yoshihara, Tsutomu

PY - 1994

Y1 - 1994

N2 - This paper describes the application of Gray code to the row decoder so that programming before erasure can be done to the defect word lines without incurring area penalty. Using this technique, a 3.3V operation 16Mb CMOS flash memory is fabricated in 0.5μm CMOS technology. The cell is 75ns at 3.3V Vcc. Process parameters and typical characteristics of the 16Mb memory are summarized. A block diagram of the chip is shown. The array is divided into 8 planes. Each plane is divided into four independently erasable 64kB blocks. There are 16 redundant WLs and 128 redundant columns. 65% of the repaired chips are confirmed by the proposed row redundancy system. Although the scheme is proven only by a limited number of devices, it apparently will be useful independent of the line level and the stage of manufacture. A micrograph of this chip is shown.

AB - This paper describes the application of Gray code to the row decoder so that programming before erasure can be done to the defect word lines without incurring area penalty. Using this technique, a 3.3V operation 16Mb CMOS flash memory is fabricated in 0.5μm CMOS technology. The cell is 75ns at 3.3V Vcc. Process parameters and typical characteristics of the 16Mb memory are summarized. A block diagram of the chip is shown. The array is divided into 8 planes. Each plane is divided into four independently erasable 64kB blocks. There are 16 redundant WLs and 128 redundant columns. 65% of the repaired chips are confirmed by the proposed row redundancy system. Although the scheme is proven only by a limited number of devices, it apparently will be useful independent of the line level and the stage of manufacture. A micrograph of this chip is shown.

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M3 - Conference contribution

AN - SCOPUS:0028015196

SN - 0780318455

SP - 150

EP - 151

BT - Digest of Technical Papers - IEEE International Solid-State Circuits Conference

A2 - Anon, null

PB - Publ by IEEE

CY - Piscataway, NJ, United States

T2 - Proceedings of the 1994 IEEE International Solid-State Circuits Conference

Y2 - 16 February 1994 through 18 February 1994

ER -

Row-redundancy scheme for high-density flash memory

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