抄録
The authors present a logic synthesis system based on a combined approach in which tables for transformation are described as rules and are applied by a rule interpreter together with a logic minimization algorithm. Physical constraints such as longest path lengths between registers, fan-in/out, and polarity are checked whenever each rule is applied. Experimental results show that the system generates solutions very close to the manual implementation, and a logic minimization algorithm reduces the circuit size by 20%.
| 本文言語 | English |
|---|---|
| ホスト出版物のタイトル | Unknown Host Publication Title |
| Place of Publication | New York, NY, USA |
| 出版社 | IEEE |
| ページ | 162-165 |
| ページ数 | 4 |
| ISBN（印刷版） | 0818607440 |
| 出版ステータス | Published - 1986 |
| 外部発表 | はい |
ASJC Scopus subject areas
- 工学（全般）