TY - GEN
T1 - Scaling scenario of floating body cell (FBC) suppressing Vth variation due to random dopant fluctuation
AU - Furuhashi, Hironobu
AU - Shino, Tomoaki
AU - Ohsawa, Takashi
AU - Matsuoka, Fumiyoshi
AU - Higashi, Tomoki
AU - Minami, Yoshihiro
AU - Nakajima, Hiroomi
AU - Fujita, Katsuyuki
AU - Fukuda, Ryo
AU - Hamamoto, Takeshi
AU - Nitayama, Akihiro
PY - 2008/12/24
Y1 - 2008/12/24
N2 - A scaling scenario of fully-depleted floating body cell (FBC) is demonstrated in view of signal margin for stable array functionality. Measurement and numerical simulation reveal that the Vth variation of cell array transistors is mainly attributed to the random dopant fluctuation in channel region. By setting the channel impurity concentration in the order of 1016cm-3 or lower, Gbit array functionality is guaranteed for the 32nm node and further scaled generations.
AB - A scaling scenario of fully-depleted floating body cell (FBC) is demonstrated in view of signal margin for stable array functionality. Measurement and numerical simulation reveal that the Vth variation of cell array transistors is mainly attributed to the random dopant fluctuation in channel region. By setting the channel impurity concentration in the order of 1016cm-3 or lower, Gbit array functionality is guaranteed for the 32nm node and further scaled generations.
UR - http://www.scopus.com/inward/record.url?scp=57749205627&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=57749205627&partnerID=8YFLogxK
U2 - 10.1109/SOI.2008.4656281
DO - 10.1109/SOI.2008.4656281
M3 - Conference contribution
AN - SCOPUS:57749205627
SN - 9781424419548
T3 - Proceedings - IEEE International SOI Conference
SP - 33
EP - 34
BT - 2008 IEEE International SOI Conference Proceedings
T2 - 2008 IEEE International SOI Conference
Y2 - 6 October 2008 through 9 October 2008
ER -