抄録
This paper proposes a novel approach for implementing an ultra-low-power voltage reference using the structure of self-cascode MOSFET, operating in the subthreshold region with a self-biased body effect. The difference between the two gate-source voltages in the structure enables the voltage reference circuit to produce a low output voltage below the threshold voltage. The circuit is designed with only MOSFETs and fabricated in standard 0.18-μm CMOS technology. Measurements show that the reference voltage is about 107.5 mV, and the temperature coefficient is about 40 ppm/°C, at a range from -20°C to 80°C. The voltage line sensitivity is 0.017%/V. The minimum supply voltage is 0.85 V, and the supply current is approximately 24 nA at 80°C. The occupied chip area is around 0.028 mm2.
本文言語 | English |
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ページ(範囲) | 859-866 |
ページ数 | 8 |
ジャーナル | IEICE Transactions on Electronics |
巻 | E96-C |
号 | 6 |
DOI | |
出版ステータス | Published - 2013 6月 |
ASJC Scopus subject areas
- 電子工学および電気工学
- 電子材料、光学材料、および磁性材料