SOI device is promised to be a mobile and wireless network applications as it has better potential of high speed, low operating voltage and Q-factor. Gate Body directly connected SOI MOSFET suppresses Sees historical effects and is promised technologies that let the logic circuitry work in ultra low voltage. Compared to Bulk-Si MOSFET, GBSOI can reduce its power supply voltage by 30%, its current by 26% and its power dissipation by 47%. However sub-Gbps level clocking circuits with ultra low voltage require the smaller PVT (process, voltage and temperature) variation. This paper presents an architecture to stabilize SOI logic circuitry against PVT variation especially under ultra low power supply voltage. Deviation of gate delay caused by PVT variation is reduced to 1.6%, while 40% with Bulk-Si. This system realizes the cell libraries whose gate delay is constant despite PVT variation. They greatly help designing circuitry especially under ultra low voltage.
|ホスト出版物のタイトル||ICCCAS 2007 - International Conference on Communications, Circuits and Systems 2007|
|出版ステータス||Published - 2008|
|イベント||ICCCAS 2007 - International Conference on Communications, Circuits and Systems 2007 - Kokura|
継続期間: 2007 7月 11 → 2007 7月 13
|Other||ICCCAS 2007 - International Conference on Communications, Circuits and Systems 2007|
|Period||07/7/11 → 07/7/13|
ASJC Scopus subject areas