TY - GEN

T1 - Simultaneous placement and global routing algorithm for FPGAs with power optimization

AU - Togawa, Nozomu

AU - Ukai, Kaoru

AU - Yanagisawa, Masao

AU - Ohtsuki, Tatsuo

PY - 1998/12/1

Y1 - 1998/12/1

N2 - This paper proposes a simultaneous placement and global routing algorithm for FPGAs with power optimization. The algorithm is based on hierarchical bipartitioning of layout regions and sets of logic-blocks. When bipartitioning a layout region, pseudo-blocks are introduced to preserve connections if there exist connections between bipartitioned logic-block sets. A global route is represented by a sequence of pseudo-blocks. Since pseudo-blocks and logic-blocks can be dealt with equally, placement and global routing are processed simultaneously. The algorithm gives weights to the nets with high switching probabilities and assigns the blocks connected by weighted nets to the same region. Thus their length is shortened and the power consumption of a whole circuit can be reduced. The experimental results demonstrate the effectiveness and efficiency of the algorithm.

AB - This paper proposes a simultaneous placement and global routing algorithm for FPGAs with power optimization. The algorithm is based on hierarchical bipartitioning of layout regions and sets of logic-blocks. When bipartitioning a layout region, pseudo-blocks are introduced to preserve connections if there exist connections between bipartitioned logic-block sets. A global route is represented by a sequence of pseudo-blocks. Since pseudo-blocks and logic-blocks can be dealt with equally, placement and global routing are processed simultaneously. The algorithm gives weights to the nets with high switching probabilities and assigns the blocks connected by weighted nets to the same region. Thus their length is shortened and the power consumption of a whole circuit can be reduced. The experimental results demonstrate the effectiveness and efficiency of the algorithm.

UR - http://www.scopus.com/inward/record.url?scp=0032218438&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0032218438&partnerID=8YFLogxK

M3 - Conference contribution

AN - SCOPUS:0032218438

SN - 0780351460

T3 - IEEE Asia-Pacific Conference on Circuits and Systems - Proceedings

SP - 125

EP - 128

BT - IEEE Asia-Pacific Conference on Circuits and Systems - Proceedings

PB - IEEE

T2 - Proceedings of the 1998 IEEE Asia-Pacific Conference on Circuits and Systems - Microelectronics and Integrating Systems (IEEE APCCAS-98)

Y2 - 24 November 1998 through 27 November 1998

ER -