Software-cooperative power-efficient heterogeneous multi-core for media processing

Hiroaki Shikano*, Masaki Ito, Kunio Uchiyama, Toshihiko Odaka, Akihiro Hayashi, Takeshi Masuura, Masayoshi Mase, Jun Shirako, Yasutaka Wada, Keiji Kimura, Hironori Kasahara

*この研究の対応する著者

研究成果: Conference contribution

7 被引用数 (Scopus)

抄録

A heterogeneous multi-core processor (HMCP) architecture, which integrates general purpose processors (CPU) and accelerators (ACC) to achieve high-performance as well as low-power consumption with the support of a parallelizing compiler, was developed. The evaluation was performed using an MP3 audio encoder on a simulator that accurately models the HMCP. It showed that 16-frame encoding on the HMCP with four CPUs and four ACCs yielded 24.5-fold speed-up of performance against sequential execution on one CPU. Furthermore, power saving by the compiler reduced energy consumption of the encoding to 0.17 J, namely, by 28.4%.

本文言語English
ホスト出版物のタイトル2008 Asia and South Pacific Design Automation Conference, ASP-DAC
ページ736-741
ページ数6
DOI
出版ステータスPublished - 2008
イベント2008 Asia and South Pacific Design Automation Conference, ASP-DAC - Seoul, Korea, Republic of
継続期間: 2008 3月 212008 3月 24

出版物シリーズ

名前Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Conference

Conference2008 Asia and South Pacific Design Automation Conference, ASP-DAC
国/地域Korea, Republic of
CitySeoul
Period08/3/2108/3/24

ASJC Scopus subject areas

  • コンピュータ サイエンスの応用
  • コンピュータ グラフィックスおよびコンピュータ支援設計
  • 電子工学および電気工学

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