TY - JOUR
T1 - Sorting-based I/O connection assignment and non-Manhattan RDL routing for flip-chip designs
AU - Zhang, Ran
AU - Watanabe, Takahiro
PY - 2015/12/1
Y1 - 2015/12/1
N2 - In modern VLSI designs, a flip-chip package is widely used to meet the higher integration density and the larger I/O counts of circuits. Recently the I/O buffers are mapped onto bump balls without changing the module placement using re-distribution layer (RDL) in flip-chip designs. In this research, a sorting-based I/O connection assignment and non-Manhattan RDL routing method is proposed for area I/O flip-chip designs. The approach initially assigns the I/O buffers to bump balls by sorting the Manhattan distance between them. Three kinds of pair-exchange procedures are then carried out to improve the initial assignment. Then to shorten the wire length, non-Manhattan RDL routing is adopted to connect the I/O buffers and bump balls. Finally some un-routed connections are ripped up and rerouted. The experimental results show that the proposed method is able to obtain the routes with shorter wire length in reasonable CPU times.
AB - In modern VLSI designs, a flip-chip package is widely used to meet the higher integration density and the larger I/O counts of circuits. Recently the I/O buffers are mapped onto bump balls without changing the module placement using re-distribution layer (RDL) in flip-chip designs. In this research, a sorting-based I/O connection assignment and non-Manhattan RDL routing method is proposed for area I/O flip-chip designs. The approach initially assigns the I/O buffers to bump balls by sorting the Manhattan distance between them. Three kinds of pair-exchange procedures are then carried out to improve the initial assignment. Then to shorten the wire length, non-Manhattan RDL routing is adopted to connect the I/O buffers and bump balls. Finally some un-routed connections are ripped up and rerouted. The experimental results show that the proposed method is able to obtain the routes with shorter wire length in reasonable CPU times.
KW - Flip-chip designs
KW - I/O connection assignment
KW - RDL routing
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U2 - 10.1541/ieejeiss.135.1535
DO - 10.1541/ieejeiss.135.1535
M3 - Article
AN - SCOPUS:84948770585
SN - 0385-4221
VL - 135
SP - 1535
EP - 1544
JO - IEEJ Transactions on Electronics, Information and Systems
JF - IEEJ Transactions on Electronics, Information and Systems
IS - 12
ER -