Sub-1 μm2 high density embedded SRAM technologies for 100 nm generation SOC and beyond

K. Tomita; K. Hashimoto; T. Inbe; T. Oashi; K. Tsukamoto; Y. Nishioka; M. Matsuura; T. Eimori; M. Inuishi; I. Miyanaga; M. Nakamura; T. Kishimoto; T. Yamada; K. Eriguchi; H. Yuasa; T. Satake; A. Kajiya; M. Ogura

Sub-1 μm² high density embedded SRAM technologies for 100 nm generation SOC and beyond

K. Tomita^*, K. Hashimoto, T. Inbe, T. Oashi, K. Tsukamoto, Y. Nishioka, M. Matsuura, T. Eimori, M. Inuishi, I. Miyanaga, M. Nakamura, T. Kishimoto, T. Yamada, K. Eriguchi, H. Yuasa, T. Satake, A. Kajiya, M. Ogura

^*この研究の対応する著者

研究成果: Paper › 査読

9 被引用数 (Scopus)

抄録

High density 6T-SRAM cell (0.998 μm²) was integrated for system-on-a-chip using enhanced 100 nm CMOS logic technology. The integration methodology included high-NA ArF lithography, optimized optical proximity correction CAD, narrow well isolation, poly-buffered shallow trench isolation and low-k dielectric technologies. This enhanced SRAM technology could be used for high speed and high density embedded memory applications.

本文言語	English
ページ	14-15
ページ数	2
出版ステータス	Published - 2002 1月 1
外部発表	はい
イベント	2002 Symposium on VLSI Technology Digest of Technical Papers - Honolulu, HI, United States 継続期間: 2002 6月 11 → 2002 6月 13

Other

Other	2002 Symposium on VLSI Technology Digest of Technical Papers
国/地域	United States
City	Honolulu, HI
Period	02/6/11 → 02/6/13

ASJC Scopus subject areas

電子材料、光学材料、および磁性材料
電子工学および電気工学

他のファイルとリンク

引用スタイル

Tomita, K., Hashimoto, K., Inbe, T., Oashi, T., Tsukamoto, K., Nishioka, Y., Matsuura, M., Eimori, T., Inuishi, M., Miyanaga, I., Nakamura, M., Kishimoto, T., Yamada, T., Eriguchi, K., Yuasa, H., Satake, T., Kajiya, A., & Ogura, M. (2002). Sub-1 μm² high density embedded SRAM technologies for 100 nm generation SOC and beyond. 14-15. Paper presented at 2002 Symposium on VLSI Technology Digest of Technical Papers, Honolulu, HI, United States.

Tomita, K, Hashimoto, K, Inbe, T, Oashi, T, Tsukamoto, K, Nishioka, Y, Matsuura, M, Eimori, T, Inuishi, M, Miyanaga, I, Nakamura, M, Kishimoto, T, Yamada, T, Eriguchi, K, Yuasa, H, Satake, T, Kajiya, A & Ogura, M 2002, 'Sub-1 μm² high density embedded SRAM technologies for 100 nm generation SOC and beyond', Paper presented at 2002 Symposium on VLSI Technology Digest of Technical Papers, Honolulu, HI, United States, 02/6/11 - 02/6/13 pp. 14-15.

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abstract = "High density 6T-SRAM cell (0.998 μm2) was integrated for system-on-a-chip using enhanced 100 nm CMOS logic technology. The integration methodology included high-NA ArF lithography, optimized optical proximity correction CAD, narrow well isolation, poly-buffered shallow trench isolation and low-k dielectric technologies. This enhanced SRAM technology could be used for high speed and high density embedded memory applications.",

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T1 - Sub-1 μm2 high density embedded SRAM technologies for 100 nm generation SOC and beyond

AU - Tomita, K.

AU - Hashimoto, K.

AU - Inbe, T.

AU - Oashi, T.

AU - Tsukamoto, K.

AU - Nishioka, Y.

AU - Matsuura, M.

AU - Eimori, T.

AU - Inuishi, M.

AU - Miyanaga, I.

AU - Nakamura, M.

AU - Kishimoto, T.

AU - Yamada, T.

AU - Eriguchi, K.

AU - Yuasa, H.

AU - Satake, T.

AU - Kajiya, A.

AU - Ogura, M.

PY - 2002/1/1

Y1 - 2002/1/1

N2 - High density 6T-SRAM cell (0.998 μm2) was integrated for system-on-a-chip using enhanced 100 nm CMOS logic technology. The integration methodology included high-NA ArF lithography, optimized optical proximity correction CAD, narrow well isolation, poly-buffered shallow trench isolation and low-k dielectric technologies. This enhanced SRAM technology could be used for high speed and high density embedded memory applications.

AB - High density 6T-SRAM cell (0.998 μm2) was integrated for system-on-a-chip using enhanced 100 nm CMOS logic technology. The integration methodology included high-NA ArF lithography, optimized optical proximity correction CAD, narrow well isolation, poly-buffered shallow trench isolation and low-k dielectric technologies. This enhanced SRAM technology could be used for high speed and high density embedded memory applications.

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T2 - 2002 Symposium on VLSI Technology Digest of Technical Papers

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