Suppression of die-to-die delay variability of silicon on thin buried oxide (SOTB) CMOS circuits by balanced P/N drivability control with back-bias for ultralow-voltage (0.4 V) operation

H. Makiyama; Y. Yamamoto; H. Shinohara; T. Iwamatsu; H. Oda; N. Sugii; K. Ishibashi; T. Mizutani; T. Hiramoto; Y. Yamaguchi

doi:10.1109/IEDM.2013.6724742

Suppression of die-to-die delay variability of silicon on thin buried oxide (SOTB) CMOS circuits by balanced P/N drivability control with back-bias for ultralow-voltage (0.4 V) operation

H. Makiyama, Y. Yamamoto, H. Shinohara, T. Iwamatsu, H. Oda, N. Sugii, K. Ishibashi, T. Mizutani, T. Hiramoto, Y. Yamaguchi

研究成果: Conference contribution

4 被引用数 (Scopus)

抄録

Small-variability transistors such as silicon on thin buried oxide (SOTB) are effective for reducing the operation voltage (V_dd). In the ultralow-V_dd regime, however, the upsurging delay (τ_pd) variability is the most important challenge. This paper proposes the balanced n/p drivability control method for reducing the die-to-die delay variation by back bias applicable for various circuits. Excellent variability reduction by this balanced control is demonstrated at V_dd = 0.4 V.

本文言語	English
ホスト出版物のタイトル	2013 IEEE International Electron Devices Meeting, IEDM 2013
ページ	33.2.1-33.2.4
DOI	https://doi.org/10.1109/IEDM.2013.6724742
出版ステータス	Published - 2013
外部発表	はい
イベント	2013 IEEE International Electron Devices Meeting, IEDM 2013 - Washington, DC, United States 継続期間: 2013 12月 9 → 2013 12月 11

出版物シリーズ

名前	Technical Digest - International Electron Devices Meeting, IEDM
ISSN（印刷版）	0163-1918

Other

Other	2013 IEEE International Electron Devices Meeting, IEDM 2013
国/地域	United States
City	Washington, DC
Period	13/12/9 → 13/12/11

ASJC Scopus subject areas

電子材料、光学材料、および磁性材料
凝縮系物理学
電子工学および電気工学
材料化学

文献へのアクセス

10.1109/IEDM.2013.6724742

他のファイルとリンク

フィンガープリント

「Suppression of die-to-die delay variability of silicon on thin buried oxide (SOTB) CMOS circuits by balanced P/N drivability control with back-bias for ultralow-voltage (0.4 V) operation」の研究トピックを掘り下げます。これらがまとまってユニークなフィンガープリントを構成します。

引用スタイル

Makiyama, H., Yamamoto, Y., Shinohara, H., Iwamatsu, T., Oda, H., Sugii, N., Ishibashi, K., Mizutani, T., Hiramoto, T., & Yamaguchi, Y. (2013). Suppression of die-to-die delay variability of silicon on thin buried oxide (SOTB) CMOS circuits by balanced P/N drivability control with back-bias for ultralow-voltage (0.4 V) operation. In 2013 IEEE International Electron Devices Meeting, IEDM 2013 (pp. 33.2.1-33.2.4). [6724742] (Technical Digest - International Electron Devices Meeting, IEDM). https://doi.org/10.1109/IEDM.2013.6724742

Suppression of die-to-die delay variability of silicon on thin buried oxide (SOTB) CMOS circuits by balanced P/N drivability control with back-bias for ultralow-voltage (0.4 V) operation. / Makiyama, H.; Yamamoto, Y.; Shinohara, H. その他.
2013 IEEE International Electron Devices Meeting, IEDM 2013. 2013. p. 33.2.1-33.2.4 6724742 (Technical Digest - International Electron Devices Meeting, IEDM).

研究成果: Conference contribution

Makiyama, H, Yamamoto, Y, Shinohara, H, Iwamatsu, T, Oda, H, Sugii, N, Ishibashi, K, Mizutani, T, Hiramoto, T & Yamaguchi, Y 2013, Suppression of die-to-die delay variability of silicon on thin buried oxide (SOTB) CMOS circuits by balanced P/N drivability control with back-bias for ultralow-voltage (0.4 V) operation. in 2013 IEEE International Electron Devices Meeting, IEDM 2013., 6724742, Technical Digest - International Electron Devices Meeting, IEDM, pp. 33.2.1-33.2.4, 2013 IEEE International Electron Devices Meeting, IEDM 2013, Washington, DC, United States, 13/12/9. https://doi.org/10.1109/IEDM.2013.6724742

Makiyama H, Yamamoto Y, Shinohara H, Iwamatsu T, Oda H, Sugii N その他. Suppression of die-to-die delay variability of silicon on thin buried oxide (SOTB) CMOS circuits by balanced P/N drivability control with back-bias for ultralow-voltage (0.4 V) operation. In 2013 IEEE International Electron Devices Meeting, IEDM 2013. 2013. p. 33.2.1-33.2.4. 6724742. (Technical Digest - International Electron Devices Meeting, IEDM). doi: 10.1109/IEDM.2013.6724742

Makiyama, H. ; Yamamoto, Y. ; Shinohara, H. その他. / Suppression of die-to-die delay variability of silicon on thin buried oxide (SOTB) CMOS circuits by balanced P/N drivability control with back-bias for ultralow-voltage (0.4 V) operation. 2013 IEEE International Electron Devices Meeting, IEDM 2013. 2013. pp. 33.2.1-33.2.4 (Technical Digest - International Electron Devices Meeting, IEDM).

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