The conventional tools for mismatch elimination such as geometric symmetry and common centroid technology can only eliminate systematic mismatch, but can do little to reduce random mismatch and thermal-induced mismatch. As the development of VLSI technology, the random mismatch is becoming more and more serious. And in the context of Silicon on Insulator (SOI), the self-heating effect leads to unbearable thermal-induced mismatch. Therefore, in this paper, we first propose a new model which can estimate the combination effect of both random mismatch and thermal-induced mismatch by mismatch analysis and SPICE simulation. And in order to meet the different sensitivities of different symmetry pairs, an automatic classification tool and a configurable optimization process are also introduced. All of these are embedded in the floorplanning process. The final experimental results prove the effectiveness of our method.
|ホスト出版物のタイトル||Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC|
|出版ステータス||Published - 2008|
|イベント||2008 Asia and South Pacific Design Automation Conference, ASP-DAC - Seoul|
継続期間: 2008 3月 21 → 2008 3月 24
|Other||2008 Asia and South Pacific Design Automation Conference, ASP-DAC|
|Period||08/3/21 → 08/3/24|
ASJC Scopus subject areas